El Correo Libre, Issue 29

Published in

LibreCores

15 min readJul 14, 2020

Cocotb Version 1.4.0 Brings Major Improvements

Cocotb, a community project held under the umbrella of the FOSSi Foundation, is proud to announce the release of its new version 1.4.0. Cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python.

This release concludes a six month development period, similar to its predecessors in recent history. A major focus of this release was stability and ease of use.

Writing testbench code is now more intuitive than ever thanks to full support for async functions. In a nutshell: all async functions can now be used as coroutines, they no longer need to be annotated with @cocotb.coroutine.

Instead of using yield to wait for coroutines to complete, the more descriptive await can be used. Important: the old syntax is still fully supported and can be used along with the new async syntax. You can head over to the documentation for more details on the syntax and the new usage scenarios it enables.

The second major improvement in this release is our build system. Since its beginning, cocotb has shipped a make-based build system. This build system serves two goals: It compiles and installs cocotb-internal support libraries, as well as the VPI/VHPI/FLI library which is linked into the simulator at runtime.

As a second step, the build system calls the simulator in the right way to load the cocotb libraries, pass the RTL source files, and start the simulation. All cocotb users had to do to make use of this functionality is include two makefile fragments, Makefile.inc, and Makefile.sim.

With the 1.4.0 release we made building and running cocotb simulations even simpler. First of all, users now only need to include the Makefile.sim file; Makefile.inc no longer needs to be included. Under the hood, a more significant change took place: the compilation step for the binary libraries is no longer performed when running a simulation. Instead, libraries are compiled during the installation of cocotb with “pip install cocotb”.

Thanks to this change, integrating cocotb into in-house build systems is easier than ever, startup times when running simulations have been reduced, and there’s no need any more for a compiler to be present when running simulations. Even more importantly, this change paves the way to provide a better way to run cocotb simulations without make; doing so has for a long time been requested from our Windows users.

Details on additional improvements, the sponsors who supported the release, and how to get started with cocotb can be found on the FOSSi Foundation website or in the official release changelog — and if you’d like to sponsor cocotb development, please do reach out!

-Philipp Wagner, Director, FOSSi Foundation

SkyWater Production Development Kit Launches with Free Manufacturing Pledge

Announced during the inaugural FOSSi Foundation Dial-Up event in a presentation by Google’s Tim Ansell, the SkyWater Production Development Kit is now official — and comes with the offer of free manufacturing for open hardware initiatives looking to make the leap from building for field-programmable gate arrays (FPGAs) to dedicated silicon.

“The SkyWater Open Source PDK is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit and related resources,” Tim explained of the platform during his Dial-Up presentation, “which can be used to create manufacturable designs at SkyWater’s facility.”

“This is certainly a dream come true for us at the FOSSi Foundation,” director Philipp Wagner adds of the announcement. “We helped the Free and Open Source Silicon community, our community, grow and tackle huge challenges over the years. An open, manufacturable PDK was the main blocker in a fully open flow between RTL and a physical chip, and we’re extremely excited to see that blocker removed.”

The PDK is based on a well-established 180–130nm hybrid process node originally developed at Cypress Semiconductor. To support the ecosystem, Google has confirmed it will be funding several multi-project wafer manufacturing runs — covering the entire cost of production for open hardware projects — with the first scheduled to take place in November and additional throughout 2021.

Described as being in “experimental preview/alpha release” status, the PDK is available now on GitHub under the permissive Apache Licence 2.0; documentation can be found on Read The Docs. Tim’s presentation, meanwhile, is available on the FOSSi Foundation YouTube channel.

QuickLogic Launches QuickFeather Open FPGA Crowdfunder

QuickLogic has officially opened a crowdfunding campaign for the QuickFeather, an FPGA development board built around the company’s EOS S3 system-on-chip (SoC) and targeting low-power embedded projects.

“As part of our recently announced QuickLogic Open Reconfigurable Computing (QORC) initiative, we took special care to make everything about QuickFeather open source, from the hardware, to the software, to the tools,” QuickLogic explains. “The FPGA industry is ripe for the sort of change open source has to offer — QuickFeather is our way of welcoming that change!”

The toolchain behind the QuickFeather, and the EOS S3 on which it is based, is fully open — thanks to a partnership between QuickLogic and Antmicro, as well as input from the SymbiFlow community and additional assistance from Google.

The EOS S3 itself features an embedded FPGA with 2,400 effective logic cells and 64kB of dedicated memory, along with an 80MHz Arm Cortex-M4F hardware microcontroller core. The Feather-form-factor board also includes battery charging circuitry, a DPS310 pressure sensor, MC3635 accelerometer, and an IM64D130 microphone as on-board sensors.

More information is available on the Crowd Supply campaign page, where the QuickFeather is available to back at $59 per board — or, for those looking to build their own devices, a five-pack of EOS S3 chips can be purchased for $30.

FPGA Soft-Core SoC Shoot-Out Pits Projects Head-to-Head

Rik TW of hobbyist electronics site Just Another Electronics Blog (Jaeblog) has published an FPGA soft-core system-on-chip (SoC) shoot-out, putting projects ranging from the NEO430 to VexRiscV to the test.

“Often it can be very handy to have a CPU in an FPGA. Though some are sold with an integrated CPU, most are not,” Rik explains. “A popular option is to use a so called Softcore CPU, a CPU that is implemented in the FPGA’s logic. I decided to have a look at a few popular and some less popular ones to see how easy they are to use, how fast they are and which might be a good choice for a project.

“I have a few requirements any CPU must meet: 1. There must be a GCC or LLVM compiler available. 2. No vendor specific CPU, a CPU should run on all FPGAs. If possible, a simple ready to go SoC with UART, timer and GPIO is nice, but no requirement.”

The final list for testing covered VexRiscv, LEON3, PicoRV32, NEO430, ZPU, Microwatt, the OpenSPARC S1 Core, and Swerv EH1 — though the latter two had to be excluded, as they were too large to fit in the Arty FPGA development board used for testing.

Each SoC was put through a range of tests covering ease of use, performance, size, and an eye on both the language used and the licence under which it is made available.

“I liked the VexRiscv, LEON3 and NEO430 the most in terms of usability,” Rik concludes. “None of them where perfect. VexRiscv is very flexible, but lacks documentation in some areas, LEON3 probably works perfect with a commercial licence and the NEO430 lacks a debugger. But all in all, those three seem the best choices in my opinion if you need a CPU for an FPGA project.”

The full post, plus comments introducing some other projects into the mix, can be found on the Jaeblog site.

OpenPOWER Foundation Releases A2I POWER Core Under CC-BY 4.0 Licence

The OpenPOWER Foundation has officially released the A2I POWER core, an in-order multithreaded 64-bit POWER ISA core originally designed for edge-network use-cases, under a Creative Commons Attribution 4.0 licence.

“A2I has demonstrated its durability over the last decade — it’s a powerful technology with a wide range of capabilities,” says Mendy Furmanek, president of the OpenPOWER Foundation and director of POWER open hardware business development at IBM. “We’re excited to see what the open source community can do to modernise A2I with today’s open POWER ISA and to adapt the technology to new markets and diverse use cases.”

“With a strong foundation of the open POWER ISA and now the A2I core, the open source hardware movement is poised to accelerate faster than ever,” adds James Kulina, executive director at the OpenPOWER Foundation. “A2I gives the community a great starting point and further enables developers to take an idea from paper to silicon.”

Originally developed as a wire-speed processor for IBM’s PowerEN family of edge-of-network devices, the A2I POWER core later found a home inside the BlueGene/Q supercomputer family as its general-purpose processor. The core includes extensibility in the form of an optional auxiliary execution unit (AXU), designed to be tightly coupled with the core itself and ease special-purpose designs.

The core is available now on the OpenPower-Cores GitHub repository.

Cobham Gaisler Releases NOEL-V RV64 Core as Part of GRLIB-GBL 2020.2

Cobham Gaisler has now made the open-source implementation of its NOEL-V core, based on the RV64 RISC-V instruction set architecture, available as part of the latest GRLIB open IP core library release.

“We have just released the open source version of our NOEL-V RISC-V RV64 processor,” the company announced earlier this month, “implementing the instruction set architecture from RISC-V International, and made it available for customer design exploration and evaluation. The GRLIB-GPL 2020.2 release of our GRLIB IP core library also contains the necessary infrastructure around the processor.”

The latest library release includes both the NOEL-V RISC-V core and LEON5, another open-source core based on the OpenSPARC instruction set architecture. Both core as dual-issue with what the company describes as “advanced branch prediction capabilities.

At release, template designs are available for the Xilinx KCU105, VC707, and KC705 FPGA development boards; additionally, LEON5 supports the Altera C5EKIT and NOEL-V the Arty A7. “ Throughout 2020,” the company promises, “tailored versions of both LEON5 and NOEL-V will be released that require less logic resources and are adapted for implementation in mid-range FPGAs.”

GRLIB is available to download now under the GNU General Public Licence, on the Cobham Gaisler website.

zGlue Launches Open Chiplet Initiative, ChipBuilder Web API “Coming Soon”

Custom chip specialist zGlue has officially launched its Open Chiplet Initiative, in partnership with Google and Antmicro, in an effort to provide open designs and tools for chiplet development — all centred around an open file format dubbed ZEF.

“zGlue Open Chiplet Initiative is a gallery of open designs, tools, and file formats that span the chiplet ecosystem from toolsets all the way to completed designs,” the company explains. “The goal of the initiative is to lower the barrier for entry to create a collaborative environment for chiplet-based systems.

“zGlue provides a set of tools: zGlue Exchange Format (ZEF), a bring-up/testing software library (PyChipBuilder), design examples, development kits, and a central location for showcasing and distribution of open projects. Combining these tools together can empower third party designers to contribute to the initiative.

“Alternatively, designers can adopt readily-available projects as templates to kick-start their development. Browse the categories listed below for inspiration, to support your design, or even better, contribute to strengthening the community! Each design and collateral has an associated license and copyright as listed in their relevant repositories. These do include materials released under open source licenses, open hardware licenses, derivatives of open licenses, copylefts, and permissives.”

The Open Chiplet Initiative currently includes three open designs — GEM1, GEM2, and OmniChip — with a web API for the ChipBuilder platform described as “coming soon.” More information is available on the official website.

Kate Temkin’s USB Serial Device Uses Just Two Lines of nMigen Code

Developer Kate Temkin has released an open USB serial converter written in just two lines of nMigen and which requires only three input/output pins plus a single resistor to implement.

“FPGA hackers,” writes Kate on Twitter of the release. “Want to add a ttyACM-style ‘usb-serial’ converter to your design? Using only: two lines of nMigen (+ platform setup)?; three I/O pins + a resistor (or a PHY)?; as many symbols/second as your USB will let you?

“Well, here you go! ^_^”

Kate notes that the project does require some clocking and won’t work on banks where VCCIO isn’t set at 3.3V — and that there is still some supporting work to be done. “Over the next couple of days,” she writes, “I’m going to add some core-generation helpers — things that automatically take snippets like the couple of lines above and generate Verilog cores with ULPI / UTMI / raw-IO interfaces.”

More details are available in the Twitter thread, while the source code is available on the Great Scott Gadgets GitHub repository.

The Programming Foundation Announces Adoption of the RISC-V ISA

The Programming Foundation, an organisation set up to improve computing education and democratise resources, has announced that it is adopting the free and open source RISC-V instruction set architecture (ISA) — and that it will be developing its own operating system.

“The Programming Foundation commits to spreading awareness and education on computer programming and operating systems so that everyone is involved, and no one is left behind while the world advances,” the company writes. “The world has benefited from open-source and now it is the time to harness its power for the betterment of the future. At The Programming Foundation, we are in the initial stage of developing an operating system with a simple interface that runs on the open instruction set architecture, RISC-V.

“We are trying to provide this ecosystem for students from low-income families to enable themselves to educate in much-needed programming skills and the foundations of operating systems. We have taken the cause of building an operating system based on FreeBSD. After our third fundraiser, we plan on manufacturing these low-cost devices.

“We’ll raise funds and work with other nonprofits and schools to empower students in several parts of the US, and India. Eventually, we plan on doing the same in South East Asia, and Africa. This will not only help us build smarter us but also democratise the adoption of RISC-V processors.”

More information on the project is available on the official website.

Public Institutions Should Release Projects as Open Hardware, Say Scientists

CERN’s Javier Serrano and LBNL’s Carlos Serrano have partnered to pen a treatise on why — and how — public institutions should release any hardware designs they create as permissively-licensed open hardware.

“Imagine a world in which public institutions create a common pool of knowledge and technology which everybody is free to access,” the pair write. “A world in which commercial entities build upon that commons to add value and generate revenue, some of which is re-injected into the public sphere to fuel the continuous growth of the commons.

“Imagine we had a way to make this process super-efficient. Just think about the creative energy already present in public institutions: universities, laboratories, government agencies… In this opinion piece, we argue that with coordination and appropriate support, this vision can lead to an enormous boost to innovation and welfare.”

The article covers the early history of free and open source software, and describes a “similar democratisation process” currently underway for hardware — but warns of “a number of factors, including inertia and negative external incentives” which are currently blocking public institutions from participating.

The full article is available on Medium.

Sylvain Lefebvre’s Silice Offers a Language for Putting Algorithms onto FPGAs

Developer Sylvain Lefebvre has released an alpha version of Silice, an open-source programming language designed to make it as easy as possible to efficiently implement algorithms on FPGA hardware.

“Silice makes it possible to write algorithms for FPGAs in the same way we write them for processors: defining sequences of operations, subroutines that can be called, and using control flow statements such as while and break,” Sylvain writes. “At the same time, Silice lets you fully exploit the parallelism and niceties of FPGA architectures, describing operations and algorithms that run in parallel and are always active, as well as pipelines.

“Silice remains close to the hardware: nothing gets obfuscated away. When writing an algorithm you are in control of what happens at which clock cycle, with predictable rules for flow control. Clock domains are exposed. In fact, Silice compiles to and inter-operates with Verilog: you can directly instantiate and bind with existing modules.

“You do not need an FPGA to start with Silice: designs and their outputs (e.g. VGA signal) can be simulated and visualised. Silice works great with the open source FGPA toolchain (yosys/nextpnr/icestorm).”

While Sylvain has already used Silice to design everything from a small RISC-V core to soft-cores which implement the game engines from id Software’s classic shooters Wolfenstein 3D and Doom, it is described as alpha status. “Documentation is lacking, some examples are outdated or far from polished, some very important language features are missing, and many known issues exist,” Sylvain warns. “I am confident I can avoid major code breaking syntax changes, but some adjustments may be necessary.”

Silice is available now under the GNU Affero General Public License v3.0 on Sylvain’s GitHub repository.

Open-Source FPnew Transprecision Floating Point Unit Architecture Released

A team of researchers have released a paper describing FPnew, an open-source multi-format floating-point unit architecture designed for transprecision computing.

“The slowdown of Moore’s law and the power wall necessitates a shift towards finely tunable precision (a.k.a. transprecision) computing to reduce energy footprint,” the researchers explain. “Hence, we need circuits capable of performing floating-point operations on a wide range of precisions with high energy-proportionality.

“We present FPnew, a highly configurable open-source transprecision floating-point unit (TP-FPU) capable of supporting a wide range of standard and custom FP formats.”

The team demonstrate FPnew’s capabilities by using it as an extension to the RISC-V instruction set architecture supporting operations in half-precision, bfloat16, and eight-bit floating point formats in addition to single-instruction multiple data (SIMD) and multi-format operations.

“Integrated into a 32-bit RISC-V core, our TP-FPU can speed up execution of mixed-precision applications by 1.67x w.r.t. an FP32 baseline, while maintaining end-to-end precision and reducing system energy by 37%,” the researchers find.

“We also integrate FPnew into a 64-bit RISC-V core, supporting five FP formats on scalars or 2, 4, or 8-way SIMD vectors. For this core, we measured the silicon manufactured in GlobalFoundries 22FDX technology across a wide voltage range from 0.45V to 1.2V. The unit achieves leading-edge measured energy efficiencies between 178 Gflop/sW (on FP64) and 2.95 Tflop/sW (on 8-bit mini-floats), and a performance between 3.2 Gflop/s and 25.3 Gflop/s.”

The full paper is available for open access on arXiv.org now.