El Correo Libre — Issue 3

Describing himself in his Twitter profile as a hardware verification architect, Luke Valenty has become a household name among FPGA enthusiasts for one very good reason: he’s the creator of TinyFPGA, a family of low-cost accessible and open hardware field-programmable gate array (FPGA) development boards. Costing between $12 and $38 depending on capabilities, the boards have proven extremely popular among both enthusiasts taking their first steps and professional hardware engineers looking for fully open boards on which to develop and tinker.

Luke can attest to growing interest his low-cost accessible FPGA development boards, which speaks to increasing numbers of newcomers becoming interested in FPGA development in general. “I have seen steadily increasing interest in the entire line of TinyFPGA boards,” he explains. “The Crowd Supply campaign for the TinyFPGA BX is going very well, and people continue to buy the A1, A2, and TinyFPGA Programmer boards.

“I have a new TinyFPGA EX board in development that uses the Lattice ECP5 FPGA. I finally got the prototype boards back and have them all up and running. These boards are very exciting as they include a micro SD card slot, 64 megabits of HyperRAM, 64 megabits of SPI flash, lots of user IO, the TinyFPGA USB Bootloader, and relatively large ECP5 FPGAs.”

Asked for a list of his favourite TinyFPGA projects, Luke details creations from an audience exhibiting a wide range of interests and levels of experience. “I’ve been seeing a lot of cool projects from both beginners and FPGA veterans,” he explains. “Here are my favorites that have come to my attention: Micropython running on a PicoRV32 in a TinyFPGA B2 board; Simple VGA controller running on a TinyFPGA A1; Ben Eater/SAP inspired computer running on a TinyFPGA A2 and Microwavemont FPGA board; Pong game developed using IceStudio and no microcontroller running on a TinyFPGA B2; and an Apple I computer running on a TinyFPGA B2.”

Those eager to speak to Luke in person about his creations are in luck: “I will be exhibiting at Maker Faire Bay Area 2018 from May 18–20,” he says. “Between the TinyFPGA BX Crowd Supply campaign and getting ready for Maker Faire I hope to have some cool giveaways for visitors.”

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This Month in Open Silicon

OnChip’s Itsy-Chipsy Aims for Sub-$100 ASIC Production

Colombia-based OnChip has announced progress in its efforts to drive down the cost of application specific integrated circuit (ASIC) production at extremely low quantities, launching a block-based platform to which custom silicon can be added to produce ICs priced below $100.

“Five thousand dollars budget for a college in a developing country might be a big number. It is definitely a huge number for a tinkerer or an engineer student ambitious enough to leap from the discrete world to the integrated planet,” the company explains of its inspiration. “A service capable to deliver a chip for hundred dollars would break a paradigm and place a bridge to a community always hungry of new chips.

“With this [Itsy-Chipsy] chip platform, we paved the way to a multi-block service — like OSH Park — capable to offer silicon area for your own chip, for as low as hundred dollars,” the company’s latest announcement explains, charting a roadmap that will see the second-generation prototypes demonstrated from September this year at a cost of $100 per chip on a 180nm CMOS node.

More information is available from the project’s Hackaday page.

First Photolithographic Homemade IC Unveiled

An effort by engineer Sam Zeloof to produce an integrated circuit in a home lab using a fully photolithographic process has borne fruit, resulting in a homebrew dual differential amplifier DIP packaged chip.

“When I set out on this project I had no idea of what I had gotten myself into, but in the end I learned more than I ever thought I would about physics, chemistry, optics, electronics, and so many other fields,” writes Sam of his project. “Furthermore, my efforts have only been matched with the most positive feedback and support from the world; I owe a sincere thanks to everyone who has helped me, given me advice, and inspired me on this project. Especially my amazing parents, who not only support and encourage me in any way they can but also give me a space to work in and put up with the electricity costs… Thank you!”

Dubbed the Z1, Sam’s chip builds on work carried out by fellow engineer Jeri Ellsworth to create homebrew transistors and logic gates but replaces the epoxy hand wiring with a full 66-step photolithographic production process involving a fibre laser, a hydrofluoric acid dip, cleaning, thermal oxide growth, patterning, masking, exposure, baking, doping, aluminium sputtering, more patterning, and a hot phosphoric acid bath.

According to Sam, the yield of his home semiconductor fabrication facility is as high as 80 percent — though this “is largely dependent on my coffee intake that day,” he jokes.

Sam has detailed write-ups of his fabrication adventure on his personal blog.

PULP Platform Celebrates its Fifth Birthday

The PULP (Parallel Ultra Low Power) Platform, a joint project between ETH Zürich and the University of Bologna turned five this month, marking the occasion with a retrospective look at its releases and achievements in that time.

“It has been exactly 5 years since Luca Benini started the PULP (Parallel Ultra Low Power) project in a meeting attended by a handful of people squeezed in a tiny office in the University of Bologna,” recalls Frank K. Gurkaynak, director of the Microelectronics Design Centre at ETH Zürich. “In the 5 years since we launched the PULP Project, we have developed and tested more than 20 ASICs [Application Specific Integrated Circuits] in various technologies.

“We are expecting our latest chip, Poseidon, in Globalfoundries 22FDX technology back from manufacturing any moment. The HDL code for the PULP based blocks used in this chip is already available for everyone to use on our GitHub page (just to clarify: at the moment licensing restrictions allow us to provide only HDL code), giving everyone who is interested access to silicon proven IP.

“There are still many skeptics of the open source hardware movement, and I will not be able to convince everyone that open source hardware has a future. However I can tell you that, as the main PULP development team at ETH Zurich and University of Bologna we are committed to continue to support high-quality open source hardware and we are in discussions on participating several exciting projects that we hope to be able to announce soon.”

Frank’s full piece, and a supporting video, can be found on LinkedIn.

Hennessy, Patterson Declare “A New Golden Age for Computer Architecture”

John L. Hennessy and David A. Patterson, joint recipients of the 2017 ACM A.M. Turing Award for their pioneering work on a systematic and quantitative approach to the design and evaluation of computer architectures, have confirmed they will be giving the Turing Lecture at the International Symposium on Computer Architecture (ISCA) 2018 conference. The lecture’s title: A New Golden Age for Computer Architecture.

“We’re on the cusp of another Golden Age that will significantly improve cost, performance, energy, and security,” the pair claim in the lecture synopsis, which highlights free and open architectures and implementations as one of the key driving forces. “Unlike the past, open ISAs are viable because many engineers for a wide range of products are designing SOCs [System on Chips] by incorporating IP [Intellectual Property] and because Arm has demonstrated that IP works for ISAs [Instruction Set Architectures].

“An open architecture also enables open-source processor designs for both FPGAs and real chips, so architects can innovate by modifying an existing RISC-V design and its software stack. Given the plasticity of FPGAs, the RISC-V ecosystem enables experimental investigations of novel features that can be deployed, evaluated, and iterated in days rather than in years. That vision requires more IP than CPUs, such as GPUs, neural network accelerators, DRAM controllers, and PCIe controllers. The stability of process nodes due to the ending of Moore’s Law make this goal easier than in the past. This necessity opens a path for architects to have impact by contributing open-source components much as their software colleagues do for databases and operating systems.”

The lecture will take place during ISCA 2018 on the evening of Monday the 4th of June 2018. Entry is free, and conference registration is not required. More information is available from the conference website.

RISC-V Foundation Launches Processor Trace Group

The RISC-V Foundation has announced the launch of a Processor Trace Group, with the aim of creating a standardised hardware interface to the RISC-V core along with a data format for trace encoding.

Chaired by UltraSoC’s Gajinder Panesar and Ashling’s Hugh Okeeffe, the Group’s inaugural meeting is set to be held at the RISC-V Workshop in Barcelona following the announcement of its creation late last month.

“The group shall standardise both a hardware interface to the RISC-V core and a packet/data format which will enable the development of commercial and open source trace encoders to be supported by any tools vendors,” the Group’s charter explains. “The interfaces are to provide enough information for: a. Instruction Trace. The interfaces should be suitable for in-order and out-of-order cores with extensions.

“The group will standardize the data format for: a. Compressed branch trace so that program flow can be reconstructed by debugging tools. The group’s progress shall be evaluated after one year at which time the charter may be revised if necessary to narrow the scope of effort.”

Gajinder has confirmed that a number of parties have expressed interests in working with the group, with more information available on the RISC-V Software Development mailing list.

Dell, Fujitsu Begin Shipping FPGA-Equipped Servers

Dell and Fujitsu have confirmed the importance of core IP running on flexible FPGA hardware in the data centre, rather than exclusively in the lab as a stepping stone towards ASIC creation, launching server hardware featuring FPGAs from Intel’s recently-acquired Stratix subsidiary.

“We are at the horizon of a new era of data center computing as Dell EMC and Fujitsu put the power and flexibility of Intel FPGAs in mainstream server products,” claims Reynette Au, vice president of marketing for the Intel Programmable Solutions Group, of the partnerships, which see the servers ship with Intel Programmable Acceleration Cards preinstalled. “We’re enabling our customers and partners to create a rich set of high-performance solutions at scale by delivering the benefits of hardware performance, all in a software development environment.”

While, naturally, Intel’s focus is primarily on acceleration of data centre workloads through the use of proprietary custom core IP, an increase in the use of FPGA for acceleration duties will likely have a knock-on effect when it comes to increasing the use of open core IP.

More information is available from Intel’s press site.

Kevin Hubbard Releases Verilog RTL HyperRAM Interface

Electrical engineer Kevin Hubbard has released an open-source register transfer level (RTL) interface, written in Verilog, for the Cypress 64 megabit HyperRAM memory module, alongside a dual-PMOD adaptor board.

Designed primarily for embedded use, Cypress’ HyperRAM features an integrated refresh controller, significantly simplifying its integration. Announced on Kevin’s Twitter account, the open source Verilog code implements a simple DWORD burst interface to a 64 megabit HyperRAM module which can be installed on Kevin’s adapter board for use with a dual-PMOD physical connection to the host device.

“I’m working on an extension to [the] SUMP2 Logic Analyzer for storing samples to 64Mbit HyperRAM in parallel with on-chip FPGA Block RAMs,” Kevin confirms of his next project. “Called ‘Deep SUMP’. Stay tuned.”

Kevin’s work has already found a use in Greg Davill’s project to build a core for image capture from a longwave infrared camera. “We didn’t actually coordinate this,” Kevin explains. “I just happened to finish my IP about the same time he was bringing up his new HW.”

Kevin’s Verilog code and Gerber PCB design files can be found on the Black Mesa Labs GitHub repository, while the board can also be ordered via OSH Park.

SeL4 Microkernel Gets Early RISC-V Port Release

The first general-purpose kernel to have been proven to match specification via formal verification methods, seL4, came with a surprise in its v9.0.1 release: a functional, though prototypical, port to the open RISC-V instruction set architecture, the first open ISA supported by the kernel.

Developed by the Australian National Information and Communications Technology (ICT)’s Research Centre of Excellence (NICTA) and now maintained by Data61’s Trustworthy Systems Group, seL4 is an offshoot of Jochen Liedtke’s L4 microkernel with a focus on security through simplicity and formal verification — making it a good partner for RISC-V.

“RISC-V, through its openness and greenfield design, provides an opportunity for re-thinking the hardware-software stack. The open architecture, which is designed by leading architects and has strong industry support, is an ideal platform for our open-source seL4 system,” Data61’s Professor Gernot Heiser explains during an interview with industry news outlet Computerworld regarding the RISC-V port. “We anticipate the combination of seL4 and RISC-V to provide a compelling security solution for the next-generation Internet of Things and cyber-physical systems.”

More details on the port, which has not yet undergone formal verification, can be found in the release notes.

Quokka FPGA Toolkit Enjoys First Official Release

Quokka Robotics’ Evgeny Muryshkin has announced the first formal release of the Quokka FPGA Toolkit, a C#-based tool and language for generating VHDL.

“The Quokka project is aiming to bring software and hardware people together to create amazing integration products,” Evgeny explains. “Working with low-level hardware is a pain due to tooling, timing, synchronisation, protocol implementations, etc. There are IPs available for different tasks, but bringing it all together is a challenge which is a costly and time-consuming process. Quokka FPGA Toolkit is focused on solving this last-mile problem. It allows [you] to quickly shuffle your hardware configuration, coordinate components, and does all the heavy lifting of VHDL programming.”

Evgeny has released the source code for the Quokka Toolkit’s test cases, functional capabilities, and example designs for evaluation on his GitHub repository, though warns that the Toolkit itself — which is compatible with any operating system on which .NET Core 2.0 is installed and available — is not open source.

Informa, RISC-V Foundation Announce First Silicon Valley Summit

The RISC-V Foundation has announced a partnership with Informa’s Knowledge and Networking Division, headed by Andrew Mullins (pictured), to run the first in a planned series of annual summits in Silicon Valley’s Santa Clara Convention Centre this December.

“The RISC-V ISA has seen impressive ecosystem growth since the inception of the RISC-V Foundation, resulting in increased interest in expanding our yearly event schedule to more locations and different program formats,” explains RISC-V Foundation executive director Rick O’Connor of the new event. “To do so, it was imperative the Foundation collaborate with experts to manage the RISC-V global event series. The Foundation is pleased to partner with the KNect365 team and leverage their experience and leadership to run our upcoming events from start to finish.”

The RISC-V Summit is planned to act as the principle international event in the calendar for RISC-V promotion, and will include a multi-track conference, tutorials, and exhibitions between the 3rd and 5th of December 2018.

More information is available from the official announcement.

Tobias Whelp on FPGA RTL Checking

Software architect and OneSpin Solutions engineering manager Tobias Whelp has partnered with Semiconductor Engineering to release a video presentation on checking the register transfer level (RTL) within an FPGA against what was originally developed.

Part of Semiconductor Engineer’s Tech Talk series, Tobias’ roughly-15-minute presentation discusses the major reasons for why what is running on a given FPGA may not always match what was created by the design engineers and how to track down when this is the case.

While Tobias’ presentation makes reference to his company’s 360 EC-FPGA product, the video is nevertheless of interest to those developing on or otherwise working with FPGA-based hardware.

The video, and a follow-up comment by Tobias, is available over on Semiconductor Engineering now.

Rambus Launches RISC-V Based CryptoManager Root of Trust

Rambus has become the latest company to launch a product based on the open RISC-V instruction set architecture, using it as the basis for a security core it calls the CryptoManager Root of Trust.

“The fundamental pillars of architectural design freedom, secure processing siloed away from general processing, and layered security with a root of trust designed for multiple security layers, are unique to the CryptoManager Root of Trust design and enable easy implementation with the highest levels of protection,” explains Bret Sewell, senior vice president and general manager of Rambus’ security division, of his company’s RISC-V-based design. “The CryptoManager Root of Trust also embeds features that enable semiconductor manufacturers and device OEMs to insert hardware keys, and enables IoT service providers to manage IoT endpoints throughout their lifecycle in the field.”

“The Meltdown and Spectre flaws revealed a new class of vulnerabilities as common processors employ acceleration techniques like speculative execution to improve processing performance,” adds Rick O’Connor, executive director of the RISC-V Foundation, in explanation of Rambus’ decision to implement RISC-V and the company’s praise of the architecture’s open nature. “With solutions like the Rambus CryptoManager Root of Trust, the extensible RISC-V ISA enables developers to build connected products with a fundamentally more robust approach to security.”

More information on the CryptoManager Root of Trust, which is not itself open, is available on the official product page.

Whitequark Research, Andrew Wygle Release Glasgow Debug Tool

Whitequark Research and Andrew Wygle have released Revision A of the Glasgow, an FPGA-based debug tool built to offer multiple functions with hardware reconfiguration in a fully open design.

“Glasgow is a 50 MHz 1V8/2V5/3V3/3V6/5V0 bus multitool,” explains Whitequark of the project. “Think Bus Pirate + Bus Blaster + Logic Sniffer, all in one reconfigurable package. You have 16 pins. Put any of {JTAG,SWD,SPI,I2C,USART,…} on any of them, or even use your own protocol core on the FPGA! Glasgow has an emphasis on FOSS (open hardware + open toolchains), lower cost, and targets people who at some point are likely to want to go down to gateware level.”

Described in its source code as alpha-status, the Glasgow Revision A release is now available from the project’s GitHub repository with hardware design files, case design files, and software source code included in the bundle.

FOSSi Foundation Releases Code of Conduct

The Free and Open Source Silicon Foundation (FOSSi Foundation) now has an official Code of Conduct, which applies to all its spaces from electronic chats through to in-person meetings and conferences.

Based on the popular Apache Code of Conduct, the new FOSSi Foundation CoC aims to make Foundation activities as welcoming, open, collaborative, understanding, and inclusive as possible. Its basic tenets are: openness, empathy, collaboration, inquisitiveness, taking care in word choices, concision, and consideration for other members past, present, and future.

Full details on the Code of Conduct, including how to address perceived breaches, can be found on the official Foundation website.

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