El Correo Libre Issue 31

Published in

LibreCores

13 min readSep 8, 2020

FOSSi Dial-Up is a Blockbuster

FOSSi Dial-Up has been running for three episodes now and it was a great joy and success. In this edition of ECL I want to quickly recap what has happened so far and where you can binge the previous three episode.

In our kick-off Tim Ansell as the project lead of the Skywater open source PDK gave an overview of the project. The PDK is a major missing link in an open source silicon design flow, and this project is a thrilling milestone. If that was not enough for you, Tim announced that they will sponsor 40 designs in a shuttle run later this year. You can find our summary here.

In the second episode Mohamed Shalan announced OpenLane : An automated RTL-to-GDSII flow based on existing open source EDA tools. It can be used to generate designs using the Skywater open source PDK.

In the third episode Mohamed Kassem then gave an overview about the RISC-V based chip designs they have successfully taped out. He also announced more details about the open shuttle program.

In the next episode, James Stine will present the standard cell library for the open source PDK, followed by Matt Guthaus who presents OpenRAM support. This first batch of speakers rounds up the topic with Tim Edwards who presents Magic tool support for the PDK.

I have been moderating the events and it has been a great joy, I am always thrilled about the quality and novelty of the content. We are grateful for all the positive feedback we have received for the event series and are working on the schedule for 2021.

See you on the next FOSSi Dial-Up!

-Stefan Wallentowitz, Director, FOSSi Foundation

Imagination Technologies Announces RVfpga, a RISC-V Computer Architecture Course

Imagination Technologies, creator of the PowerVR graphics IP family and former owner of the MIPS instruction set architecture (ISA), has announced the launch of a university-level course in computer architecture — centred around the free and open-source RISC-V instruction set architecture.

“RISC-V is transforming processor design and software/hardware co-design,” says Professor David Patterson, who shares the ACM A. M. Turing Award with John Hennessy for their contributions to RISC. “RISC-V is an open architecture, which enables open-source hardware implementations. This new option means that software development can occur alongside hardware development, accelerating the design path.

“The RVfpga course enhances the understanding of not only RISC-V processors but also the RISC-V ecosystem and RISC-V SoCs. This course provides a deep understanding of an industrial-strength processor architecture and system of increasing popularity, which will prove useful to students throughout their academic and industry careers.”

“RISC-V is real and will pervade every computing level in the next five years. Its openness has enabled designers at all levels to get involved with processors without having to worry about licensing at the early stages of design,” adds Imagination’s Robert Owen. “This is empowering a new generation to experiment! Up to now, academic activity has been focused on SoC design. This course is the first to provide the all-important foundation of understanding of the components of the RISC-V ‘engine’ and how they come together. I am delighted that the Imagination University Programme has led the creation of these materials.”

The course has been developed in partnership with Associate Professor Sarah Harris, co-author of Digital Design & Computer Architecture, and Associate Professor Daniel Chaver. “When I was approached by Imagination to collaborate on creating this course,” notes Harris, “I was excited to bring a higher level of understanding of the technology to a wider audience, helping them get hands-on experience so that they can shape the future of computer architecture.”

The course centres around the CHIPS Alliance’s FuseSoC-based SweRVolf system-on-chip (SoC), which is powered by the Western Digital SweRV EH1 RISC-V core. It includes an instructor’s guide, student manual, ten labs, test materials, sample exam questions, and all IP, software, and source files.

More information is available on the official announcement.

Lattice Semiconductor Launches “Community Sourced” Portal

FPGA specialist Lattice Semiconductor has launched a new portal, “Community Sourced,” which aims to shine a spotlight on free and open source hardware projects built around its FPGA products.

“In addition to proprietary boards developed by Lattice and other partners there is a broad array of boards developed by the open source community,” the company’s newly-launched portal reads. “In some cases just the designs are available and in other cases there are sources available for purchasing assembled boards.

“For your convenience we list some of the more popular and interesting Community Sourced boards on the Lattice website. Lattice does not evaluate or certify community sourced boards so you will want to make your own assessment as to fitness for your application.”

The portal takes the form of two lists of projects: the first list covers what the company classes as “development kits and boards,” while the second are classified as “reference designs.” Each project is tagged and searchable both in the Community Design portal itself and in a full-site search of the Lattice website — appearing, impressively enough, right next to Lattice’s own evaluation and development board products.

Projects highlighted on the portal at present include the Sutajio Kosagi Fomu, 1BitSquared iCEBreaker, Greg Davill’s OrangeCrab, Matt Venn’s Basic ECP5 Dev Board, and the myStorm BlackIce-II. Those looking to see their own projects highlighted can submit details on a form to be considered for inclusion.

The Community Sourced portal is live now on the Lattice Semiconductor website.

Open-Source V8 Engine Port Brings JavaScript to RISC-V, Seeks Community Participation

A joint project between Futurewei Technologies and the RIOS Lab has resulted in the release of v8-riscv, an open-source 64-bit RISC-V backend for the popular V8 JavaScript engine — and the organisations are now looking for community assistance in taking the project to the next level.

“V8-riscv enables the complete functionality of V8 (including the Turbofan compiler, the Ignition Engine and the WebAssembly compiler) for any RISC-V ISA that supports RV64I, M, A, F, D, and Zifencei extensions,” Zhangxi Tan and Peng Wu explain in a joint statement. “The functional completeness of a V8 port is measured by the coverage of the extensive set of V8 test cases. Currently, v8-riscv passes over 15,000 standard v8 test cases as well as standard benchmarks such as Sunspider and Kraken on HiFive Unleashed running Fedora Developer Rawhide.

“The open-sourcing of v8-riscv pushes our porting effort to a new phase of community participation. There is still plenty of work ahead in bringing a high-performing V8 engine that leverages the full capability of a highly customizable RISC-V ISA. For the next few months, we would like to focus on upstreaming to V8, improving the performance of the 64-bit backend, and supporting or experimenting with additional RISC-V extensions such as C, V, and the upcoming J extensions.

“We invite any community members who would like to contribute to V8 on RISC-V to join our effort,” the pair add. “We already have a good story to share: within the first week of open-sourcing v8-riscv, the PLCT lab of Chinese Academy of Sciences, who has worked on another independent port of V8 for RISC-V, decided to consolidate the porting effort and join v8-riscv.”

More information on the release can be found on the RISC-V Foundation website; those looking to get involved should consult the project roadmap and contribute via the project’s GitHub repository.

RIOS Lab Announces PicoRio, a Raspberry Pi-Like Open-Hardware Single-Board Computer

RIOS Lab has confirmed plans to launch an open-hardware single-board computer based on the free and open source RISC-V instruction set architecture (ISA), with a variant to include graphics IP from partner Imagination Technologies.

Announced during the RISC-V Global Developer Forum earlier this month, with the full presentation not yet publicly available, the board is reported by CNX Software to include four Linux-capable RV64GC processor cores running at 500MHz or higher, an RV32IMC management core, support for LPDDR4 memory, and multiple peripheral buses, all in a device which will be opened up from the SoC itself through to the package design, board, and software under a “BSD-like” licence — though this will not include the memory and IO interface IP.

The initial variant of the board’s SoC, which could launch before the end of the year, will be joined in 2021 by a follow-up which includes graphics IP from RIOS partner Imagination Technologies. Dubbed the PicoRio GPU, full details have not been released.

The organisation has indicated it is looking to target the same budget-friendly price point as the Raspberry Pi family — which could mean a Linux-capable open-hardware RISC-V board for as little as $35, should it hit its goal.

More details will be available on the RIOS Lab website in the near future.

Ultraembedded Demonstrates a Hardware-Free Digital Audio Hack — Using On-Board LEDs

Ultraembedded has come up with a neat trick for quickly getting digital audio out of any FPGA with a user-controllable on-board LED, no additional hardware required — by turning it into an S/PDIF output.

“Want to test some audio on your FPGA, but don’t have any audio output devices/connectors? LEDs to the rescue,” ultraembedded writes via Twitter. “Playing an MP3 using SPDIF over optical on a @DigilentInc Arty A7 with my RISC-V and audio IPs.”

The trick works by turning the on-board LED, usually used simply as a status indicator, into the transmitter of an S/PDIF optical digital audio signal. By taking an optical cable connected to an S/PDIF-capable decoder and amplifier and placing the free end over the LED, the signal can be captured, decoded, and amplified.

A video of the system in action is available on Twitter; the source behind the project, meanwhile, can be found on ultraembedded’s GitHub in the riscv, core_audio, and core_dvi_framebuffer repositories.

Sylvain Lefebvre Releases Silice Update, Adds Fomu, ULX3S Support

Developer Sylvain Lefebvre has updated the Silice language, designed to make it easy to create algorithms for FPGA hardware and the technology which underpins his Wolfenstein 3D and Doom engines-in-hardware projects, adding support for the Fomu and ULX3S FPGA board among other enhancements.

“Silice master update,” Sylvain posted to Twitter by way of announcement. “ULX3S support + demo; SDCARD + OLED/LCD demos; yosys + Quartus for CycloneV (with the help of @ravenslofty); framework for FOMU contributed by rob-ng15; projects improvements, e.g. doomchip; better FSMs, local vars, linter, etc.

“In the coming weeks I’ll be focusing on resolving issues and implementing new language features in Silice. Stay tuned!”

Licensed under the AGPL-3.0 licence, Silice is presently in alpha status and active development with the aim to allow users to “ write algorithms for FPGAs in the same way we write them for processors: defining sequences of operations, subroutines that can be called, and using control flow statements such as while and break” while at the same time letting the user “fully exploit the parallelism and niceties of FPGA architectures, describing operations and algorithms that run in parallel and are always active, as well as pipelines.”

The latest version of Silice, and full source code, can be found on the project’s GitHub repository.

Bluespec Launches RISC-V Explorer to Quickly Compare and Contrast Cores

Bluespec has launched a tool designed to make it easier to find a suitable RISC-V core for any given project, starting with a hand-picked selection of RV32 and RV64 cores and soon to expand with additional projects.

“Companies around the world are acting on the new freedom to innovate with RISC-V, but many are overwhelmed by the sheer number of RISC-V offerings and the inability to compare them in a common framework,” claims Bluespec chief executive Charlie Hauck. “The RISC-V Explorer will produce better results and save years of effort over do-it-yourself evaluations.”

The RISC-V Explorer tool features pre-tested and pre-built RISC-V cores which are ready-to-run, allowing for immediate compilation and execution of a program. Bluespec has also confirmed plans to add hardware support in a future release, allowing the use of the Arty A7–100T FPGA development board.

Cores featured in the initial release include the Piccolo, Flute, and Rocket RV32 and RV64 cores, the Shakti C-Class RV32IMFC core, the SweRV RV32IMC, and the PicoRV32 RV32IMC. Bluespec has indicated that future releases will include the CV32 from the OpenHW Group, Chromite from Incore, and the company’s own Magritte.

RISC-V Explorer is available free of charge from Bluespec’s website.

Trenz’ ZynqBerryZero Packs a Xilinx FPGA into a Raspberry Pi Zero Form-Factor

The ZynqBerryZero, from Trenz Electronics, is designed to be an extremely compact FPGA development board — borrowing, as it does, the Raspberry Pi Zero gumstick-style form-factor to host a Xilinx Zynq-7000 series FPGA.

Brought to our attention by CNX Software, the ZynqBerryZero is a follow-up to 2017’s ZynqBerry which used the larger Raspberry Pi Model B form factor. At the board’s heart is a Xilinx Zynq XC7Z010–1CLG225C FPGA with 28k logic cells, 2.1Mb block ram, and 80 DSP slices, plus a dual-core Arm Cortex-A9 processor running at 666MHz.

There’s 512MB of DDR3L SDRAM, 16MB of flash storage expandable via microSD, a mini-HDMI connector, a CSI-2 camera connector, a micro-USB 2.0 port, a second micro-USB 2.0 port for JTAG and UART connectivity, and a 40-pin GPIO header which borrows the Raspberry Pi pinout.

The company is selling the ZynqBerryZero for €99 plus taxes on its web store; more information is available on the product wiki.

Government of India Launches Swadeshi Microprocessor Challenge

The Government of India has launched a challenge for स्वदेशी (swadeshi) compute hardware — an effort to do for microprocessors what the movement did for the independence of India itself, by encouraging the development of home-grown technology based on open source technology.

“There is a growing need for Swadeshi Compute Hardware, that shall be part of every Smart Device deployed in different domains, including Electronics for public utility services such as Surveillance, Transportation, Environmental condition monitoring, to commodity appliances like smart fans/ locks/ washing machines,” the government explains of the project.

“In addition, with growing penetration of smart electronics in strategic areas including Space, Defence and Nuclear energy, the need for Swadeshi Compute Hardware is crucial. It is not just the cost or embargo that drives this need, but also the dependence on external vendors, long term sustenance, quick enhancements to suit the ever-growing requirements, and most-importantly Security.”

The Swadeshi Microprocessor Challenge is open to all Indian nationals working on projects using the Shakti core from IIT Madras or the VEGA core from C-DAC on Arty A7–100T or Arty A7–35T development boards, providing they do not work for a company with a revenue over 100 crore rupees. Entrants will be provided with support, mentorship, showcase opportunities, and cash prizes.

Full details of the competition are available on the official website.

Dan Petrisko Shows Off BlackParrot, An “Agile” RISC-V Multicore for Accelerators

A video of Dan Petrisko’s FOSDEM presentation from earlier this year has now been published, showcasing an “agile” RISC-V multicore designed for high-performance accelerator system-on-chip (SoC) use: BlackParrot.

“BlackParrot is a Linux-capable, cache-coherent RISC-V multicore, designed for efficiency and ease of use,” Dan explains. “BlackParrot aims to be the default open-source, Linux-capable, cache-coherent, RV64GC multicore used by the world.

Although originally developed by the University of Washington and Boston University, BlackParrot strives to be community-driven and infrastructure agnostic, a core which is Pareto optimal in terms of power, performance, area and complexity. In order to ensure BlackParrot is easy to use, integrate, modify and most importantly trust, development is guided by three core principles: Be Tiny, Be Modular, and Be Friendly.

“Development efforts have prioritized ease of use and silicon validation as first order design metrics,” Dan continues, “so that users can quickly get started and trust that their results will be representative of state-of-the-art ASIC designs. BlackParrot is ideal as the basis for a research platform, a lightweight accelerator host or as a standalone Linux core.”

The presentation covers the core itself, the software and hardware ecosystem surrounding it, the project roadmap, community outreach, and a demonstration of multithreading running on an FPGA implementation of BlackParrot.

The video is available now on the FOSDEM YouTube channel.

FOSSi News In Brief

Have feedback or news for inclusion in a future newsletter? Please send this to ecl@librecores.org.

Subscribe to get El Correo Libre direct to your inbox.