Antmicro Integrates Embench for Quick Core-to-Core Performance Comparisons
Free and open source silicon pioneer Antmicro has published a series of benchmark results designed to pit a selection of cores head-to-head in real-world workloads, using the Embench benchmark suite maintained by the FOSSi Foundation.
“Embench, maintained by the FOSSi Foundation we proudly participate in, is an open source embedded benchmark test suite which aims to respond to the needs of modern embedded systems,” the company explains of its choice to use Embench. “It is free (as in both ‘beer’ and ‘freedom’ — you can get it from GitHub), easily portable, simple to use and provides a set of real programs, as opposed to the synthetic workloads offered by some of its proprietary counterparts.
“This allows it to accurately reflect how the tested CPU is going to behave once implemented in hardware. Being a suite rather than a single program, it allows the user to do tests with a complex, realistic workload and is easy to develop to accommodate the changes in compilers and hardware.”
Antmicro has taken Embench and run it across a selection of popular free and open source silicon cores, including VexRiscV, PicoRV32, Minerva, Microwatt, and Serv, covering the RISC-V, ML32, OpenRISC, and OpenPOWER instruction set architectures. Each is run through a collection of real-world workloads including hashing, cryptographic operations, sorting, and image compression, and their performance recorded.
“Here, we’ve used Embench to compare CPUs in multiple LiteX-based SoCs in an automatic CI [continuous integration] testing flow,” the company writes. “We achieved that by creating a test suite consisting of Embench tests that runs software in a simulation environment, which is much more convenient than having to manually run multiple designs on hardware, as tests are generated automatically on a server in Continuous Integration.
“Thanks to this work, we can now quickly compare several CPUs in various specific contexts before choosing the most suitable one for any given project.”
The full results are published on Antmicro’s GitHub repository; more information on Embench itself can be found on the project website.
Precursor Packs Open Source Silicon into a Smartphone-Like Development Unit
Andrew “bunnie” Huang has announced plans to release an all-in-one smartphone-like development platform designed specifically for experimentation with free and open source silicon: Precursor.
“Precursor is a mobile, open source electronics platform,” bunnie explains. “Similar to how a Raspberry Pi or an Arduino can be transformed into an IoT gadget with the addition of a couple breakout boards, some solder, and a bit of code, Precursor is a framework upon which you can assemble a wide variety of DIY mobile applications.
“Precursor is unique in the open source electronics space in that it’s designed from the ground-up to be carried around in your pocket. It’s not just a naked circuit board with connectors hanging off at random locations: it comes fully integrated — with a rechargeable battery, a display, and a keyboard — in a sleek, 7.2 mm (quarter-inch) aluminium case.”
Precursor is an offshoot of an earlier project to build a secure mobile communication device, Betrusted. Inside the shell, inspired by classic BlackBerry mobile devices, is a Xilinx XC7S50 FPGA system-on-chip and a Lattice iCE40-UP5K embedded controller, along with Wi-Fi radio, 128MB SPI flash, 16MB of battery-backed RAM, and associated support circuitry for battery charging, driving the display, and connecting to the physical keyboard.
“Precursor comes pre-loaded with a bitstream that makes the FPGA behave like a RISC-V CPU,” bunnie explains, “but you’re free to load up (or code up) any CPU you like, be it a 6502, an lm32, an AVR, an ARM, or something else. It’s entirely up to you.
“This flexibility comes with its own set of trade-offs, of course. CPU speeds are limited to around 100 MHz, and complexity is limited to single-issue, in-order microarchitectures. It’s faster than any Palm Pilot or Nintendo DS, but it’s not looking to replace your smartphone.”
More details on the project can be found on bunnie’s blog, while a pre-registration page for a crowdfunded production run is available on Crowd Supply now.
Edalize Adds Two New Backends, Boasts 25 Supported EDA Tools
Edalize, the leading Python abstraction library for interfacing with electronic design automation (EDA) tools, has added support for two new backends — bringing the total number of tools supported to 25.
“All EDA tools such as Icarus, Yosys, ModelSim, Vivado, Verilator, GHDL, Quartus, etc get input HDL files (Verilog and VHDL) and some tool-specific files (constraint files, memory initialization files, IP description files etc),” project maintainer and FOSSi Foundation director Olof Kindgren explains. “Together with the files, perhaps a couple of Verilog `defines, some top-level parameters/generics or some tool-specific options are set. Once the configuration is done, a simulation model, netlist or FPGA image is built, and in the case of simulations, the model is also executed, maybe with some extra run-time parameters.
“The thing is, all these tools are doing this in completely different ways and there’s generally no way to import configurations from one simulator to another. Edalize takes care of this for you. By telling Edalize what files you have, together with some info, what parametrization to use at compile- and run-time (e.g. plusargs, defines, generics, parameters), VPI library sources (when applicable) and any other tool-specific options not already mentioned, it will create the necessary project files and offer to build and run it for you.”
In its latest revision, the free and open source Edalize has received support for interfacing with Lattice Semiconductor’s proprietary Radiant tool along with support for the open-source SymbiFlow toolchain — the latter launched with no lesser aim than to become “the GCC for FPGAs.”
The latest version is available on GitHub now, under the permissive BSD two-clause licence.
SHAKTI Project Celebrates Third Silicon Success with Arduino-Compatible Moushik
The SHAKTI project, which launched in 2014 as an effort to bring home-grown silicon to India’s technology industry with custom POWER architecture parts before switching to RISC-V, has celebrated its third in-silicon bring-up: A microcontroller dubbed Moushik.
“Moushik is a processor-cum-system on chip that would cater to the rapidly growing Internet of Things IOT devices that are integral part of smart cities of our digital India,” the team explains. “Three steps are involved in the making of a microprocessor chip: the design, the fabrication, and the post-silicon boot-up — all these steps were done in India.
“The design was done in IIT Madras, the fabrication at the semiconductor laboratory Chandigarh, the motherboard printed circuit board design was done again at IIT Madras, manufacturing of this motherboard at Bengaluru assembly and post-silicon boot-up at IIT Madras.”
The native processor is made in India on a 180nm process and offers 103 input/output pins connected to a SHAKTI E-Class RISC-V core running at between 75MHz and 100MHz. The chip is designed for use in a motherboard dubbed Adronics 1.0, which offers compatibility with Arduino Shield add-ons to speed development — and includes bidirectional voltage conversion, to improve compatibility still further.
More details are available on the Moushik post-silicon bring-up video and on the SHAKTI Twitter account.
iCEBreaker Bitsy v1.1a FPGA Development Boards Pass Testing
Engineer Piotr Esden-Tempski has shown off a test batch of iCEBreaker Bitsy v1.1a development boards, designed to offer a more compact alternative to the popular iCEBreaker FPGA development board.
“iCEBreaker Bitsy is the smaller but just-as-capable sibling to iCEBreaker,” the project maintainers explain. “At just 1.4x0.7in, it is compatible with the Teensy form-factor and can be easily embedded into any project.”
The iCEBreaker Bitsy is built around a Lattice Semiconductor iCE40UP5K in a QFN48 package with phase-locked loop (PLL), two SPI buses, and two I2C hard IP blocks, and features 16MB of DDR- and QPI-capable flash memory, 8MB of QPI-capable pseudostatic RAM (PSRAM), a USB Type-C interface linked to a pre-loaded RISC-V soft USB bootloder, an RGB LED, two single-colour user LEDs, a 12MHz external clock, and a single user button.
Piotr showed off an early batch of iCEBreaker Bitsy v1.1a boards on Twitch.tv and Twitter, streaming the assembly and successful test of the boards. The changes for v1.1a, meanwhile, were merged into the iCEBreaker FPGA GitHub repository back in August.
More details on both the iCEBreaker and iCEBreaker Bitsy can be found on the project’s GitHub repository.
IBM Releases A2O POWER Core, Open-CE, POWER10 Functional Simulator
IBM is continuing its push, through the OpenPOWER Foundation, into free and open-source silicon, releasing a new POWER-based core, the Open Cognitive Framework (Open-CE), and a functional simulator for POWER10 — the latter giving developers a chance to port software to the core without requiring physical hardware.
“I’m excited to announce the opening of the out-of-order A2O core design,” OpenPOWER Foundation president Mendy Furmanek told attendees during the OpenPOWER Summit 2020. “A2O provides enhanced single-thread performance and is a perfect companion to the highly scalable 4-way SMT commercialized A2I core. These, combined with the ease of entry Microwatt core, do an excellent job of showcasing the versatility of the POWER ISA.”
During the same event, IBM announced that it was opening up its PowerAI project as the Open Cognitive Environment (Open-CE) in an effort to improve the accessibility of deep-learning and artificial intelligence tools — and has teamed up with Oregon State University (OSU) to ensure that binaries are available for each release.
Shortly after the event, IBM’s Brad Thomasson announced the release of a functional simulator for the company’s latest POWER10 processor. “This publicly available simulation environment is designed to educate developers, facilitate porting of existing Linux applications to the POWER10 architecture, and enable new ones to be created,” Thomasson explains.
“This simulator provides enough POWER10 processor complex functionality to allow the entire software stack to execute. This includes loading, booting and running a little endian Linux environment.”
The functional simulator is available on the IBM website now; A2O can be found on GitHub under the permissive Creative Commons Attribution 4.0 licence, though with an addendum stating that “additional rights, including the right to physically implement a softcore that is compliant with the required sections of the Power ISA Specification” is available “at no cost” from the OpenPOWER Foundation. Open-CE is also available on GitHub, under the Apache 2.0 licence.
KAIST Researchers Publish OpenExpress, an Open Non-Commercial NVMe Controller
Researchers at the Korean national research institute KAIST have published an open-source controller for Non-Volatile Memory Express (NVMe) storage devices — though it comes with a clause preventing its use for commercial purposes.
The team developed the controller IP, dubbed OpenExpress, after finding that access to proprietary IP for research purposes would cost upwards of $34,000 per month — and so Professor Myoungsoo Jung led a team at KAIST’s School of Electrical Engineering to develop an in-house NVMe controller in both IP and physical FPGA_driven prototype form.
The research prototype has proven performant, too: the researchers claimed an impressive 76 percent increase in bandwidth and 68 percent drop in input/output latency compared to Intel’s commercial Optane flash controller.
“With the product of this study being disclosed to the world, universities and research institutes can now use controllers that used to be exclusive for only the world’s biggest companies, at no cost,” says Professor Jung. “This is a meaningful first step in research of information storage device systems such as high-speed and volume next generation memory.”
More details on OpenExpress can be found in the team’s paper submitted for the 2020 USENIX Annual Technical Conference (PDF warning); OpenExpress itself can be downloaded now from the Computer Architecture and Memory Systems Laboratory website under the OpenExpress Licence 0.1 — which allows for “academic research and non-commercial purposes” only.
Ken Shirriff Reverse-Engineers the World’s First FPGA, Xilinx’ XC2064
Noted engineer Ken Shirriff has performed another feat of reverse-engineering based primarily on die photography of silicon, and his target this time is something special: The first commercial FPGA ever made, Xilinx’ XC2064.
“The FPGA was invented by Ross Freeman who co-founded Xilinx in 1984 and introduced the first FPGA, the XC2064,” Ken writes by way of background. “This FPGA is much simpler than modern FPGAs — it contains just 64 logic blocks, compared to thousands or millions in modern FPGAs — but it led to the current multi-billion-dollar FPGA industry. Because of its importance, the XC2064 is in the Chip Hall of Fame.
“Nowadays, an FPGA is programmed in a hardware description language such as Verilog or VHDL, but back then Xilinx provided their own development software, an MS-DOS application named XACT with a hefty $12,000 price tag. XACT operated at a lower level than modern tools: the user defined the function of each logic block […] and the connections between logic blocks. XACT routed the connections and generated a bitstream file that could be loaded into the FPGA.”
Ken’s reverse engineering hasn’t just focused on the physical layout of the part, though, nor on how it works electrically — but on figuring out the format of its bitstream. “I’ve determined how most of the XC2064 bitstream is configured,” he writes, “and I’ve made a program to generate the CLB information from a bitstream file.
“Unfortunately, this is one of those projects where the last 20% takes most of the time, so there’s still work to be done. One problem is handling I/O pins, which are full of irregularities and their own routing configuration. Another problem is the tiles around the edges have slightly different configurations. Combining the individual routing points into an overall netlist also requires some tedious graph calculations.”
Full details are available on Ken’s blog, while the program is available on GitHub under an unspecified licence.
RISC-V Celebrates a Decade of Free and Open Source Silicon
The RISC-V project, one of the biggest success stories in the history of free and open source silicon, is celebrating its first decade — and the RISC-V International Association has pledged to improve the instruction set architecture for cryptography, vector processing, and code size reductions.
“Our community is now in a unique position to take advantage of the history of all that came before us in open-source software and hardware,” claims Mark Himelstein on the project’s tenth anniversary. “RISC-V is a ground-up open source architecture embodying the principles of RISC computers. It’s a flexible platform that’s appropriate for solutions targeting industry needs ranging from the Internet of Things (IoT) to supercomputers and everything in between.
“We initially developed a compact instruction set architecture (ISA) with the ability to include common, optional, and custom extensions. Not surprisingly, the bar is much higher now than when the first commercial RISC chips showed up in products in the 1980s. This means that there are more requirements for ISA features as well as the need for a growing ecosystem to produce a deployable product.”
Those requirements will be addressed, Mark explains, by the formal adoption of a number of extensions to the core RISC-V ISA targeting cryptographic workloads including AES-128, vector operations, and enhancements which reduce the code size and improve cache locality.
“With these examples, you can see that RISC-V is looking at the needs of specific industries and translating them into the appropriate RISC-V features,” Mark claims. “Such a holistic view plus RISC-V’s flexibility has attracted members from a broad set of industries. And it’s our intention to continue with this paradigm. As a result, you can one day expect to see RISC-V designs in your toaster as well as the largest supercomputers on earth and every computing platform in between.”
Mark’s full post is available on the RISC-V website.
Dan Gisselquist Releases a Firewall for your AXI Streams
Zip CPU creator Dan Gisselquist has published an open-source AXI stream firewall, designed to detect and flag incomplete data frames to assist with debugging.
“If you place this between your source and the FFT,” Dan explains, “it’ll guarantee the FFT gets full frames of data — potentially detecting and flagging faults if not. Yes, it is fully verified with SymbiYosys. Yes, even this week, there were two help requests from individuals struggling to find bugs in AXI-stream based designs.
“I’ve called these things ‘bus fault isolators’ before, but I really like the term ‘firewall.’ Uncertain protocol compliance on one side (the potential fire), and guaranteed protocol compliance (safety) on the other. i.e., a firewall.”
The firewall module presently detects three types of errors: stalls where something changes in the stream, such as a stream overflow; packets of an incorrect user-configurable length; and excess stalls. A fourth fault mode, for video streams, is suggested in the comments but not yet implemented.
The firewall code is available now on the Zip CPU GitHub repository under the permissive Apache 2.0 licence.
FOSSi News In Brief
- Proceedings of the RISC-V Global Forum — including slides and videos — now published
- Bluespec: “Designing Hardware Systems and Accelerators with Open-Source Bluespec Haskell” (video)
- Microsoft teases “Sandpiper,” a novel open-source hardware description language
- Fritzmann, Sigl, Sepúlveda: “RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography”
- lowRISC: “GSoC Projects Successfully Completed”
- RISC-V-powered Microchip PolarFire SoC Icicle development kit now available
- Protocol: Interview with RISC-V International CEO Calista Redmond
- Hardwear.io/Drew Fustini: “RISC-V: How an open ISA benefits hardware security” (video)
- SiFive announces plan to launch an off-the-shelf RISC-V-based personal computer for developers
- Rochester Institute of Technology announces Open@RIT, “a university-wide initiative for all things open”
- Harvey Mudd to offer a RISC-V-focused massive open online course based on David Harris and Sarah Harris’ Digital Design and Computer Architecture
- Semi Engineering: “RISC-V: Will There Be Other Open-Source Cores?”
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