El Correo Libre Issue 34
Looking Back on 2020, The Year of the Open-Source Chip
2020 was quite a year. Even though it played out different for each of us, we were united in that many of our plans didn’t work out. Much has been written about missed chances, but let’s end this year on a positive note and focus on the good things. After all, that’s something the software and hardware development community have always been good at: embracing change. So let’s call 2020 an “agile year” and do a “sprint recap.”
A key part of our mission as FOSSi Foundation is to facilitate the exchange of ideas. In the past, we did so mainly through our in-person conferences. For 2020, we had planned FOSSIstanbul in March, our first ever conference in Istanbul (Turkey), Latch-Up in Boston, MA (USA), and finally ORConf some time in September. As we look back, it’s no surprise that we had to cancel all of them. Early on we also decided that we wouldn’t be able to run a virtual in-person-like event with the limited resources we had.
FOSSi Dial-Up and the year of the open source chip
Instead, we launched FOSSi Dial-Up, a series of high-impact, deeply technical talks. We were very grateful to kick this series off with a talk by Tim Ansell, in which we introduced something unimaginable even a couple months back: a fully free and open source Process Design Kit (PDK), the last (major) remaining blocker to produce fully open source chips. And as if that wasn’t enough, Tim even announced free (as in beer) “shuttle runs,”opportunities to get chips produced as an individual for no cost. Read more about the SkyWater PDK effort in our blog post Produce your own physical chips. For free. In the Open, or watch the recording of Tim’s talk, as more than 18,000 people have done so far!
Subsequent FOSSi Dial-Up talks featured Mohamed Shalan, Mohamed Kassem, James Stine, Matt Guthaus, and Tim Edwards providing technical deep-dives into various aspects of chip design and manufacturing, and highlighted the challenges, but also the immense progress a relative small group of open source developers have made through their continued contributions over the years. How about that: 2020, the year of the open source chip.
Four students tipped their toes into hardware design in this year’s GSoC
Introducing more people to the world of open source hardware is another main concern of the FOSSi Foundation. As in the previous years, we have participated in the Google Summer of Code program as an umbrella organization, helping our community members to best mentor their GSoC students. After many months of hard work, four students completed their tasks. A big thank you goes out to all students and mentors who made GSoC possible in this year of uncertainty.
Cocotb pushes forward the state of the art in verification
Verification remains a challenging topic in hardware design, and we are happy that the FOSSi Foundation-supported cocotb project is making steady progress on this front. In 2020, two cocotb releases were published, with the next release expected to happen in early 2021. To keep up with the steady stream of changes the project added four new maintainers (Eric, Colin, Kaleb, and Marlon), ensuring that the project continues to operate on a healthy footing.
The SolderPad license is now easier to use
The licensing committee released an updated version of the SolderPad hardware license with minor clarifications, and added it to the SPDX list of licenses.
Embench is working on including floating point tests
Embench, the embedded benchmark suite and another FOSSi Foundation project, saw a steady stream of improvements, and a version 0.6 is work in progress, including floating point tests.
Thankfully looking forward
Overall, even though 2020 didn’t go as planned in many aspects, it wasn’t a wasted year: we saw that the steady push towards free and open source silicon isn’t all glamourous at times, but when the time is right, great things happen: the SkyWater PDK is one such example, and we’re all excited to see more such stories in the months and years to come.
A big thank you goes out to all people involved in the FOSSi Foundation and in free and open source hardware projects. You are amazing! Keep up the great work! A special thank you this year goes out to Frank Gürkaynak, who was primary organizer for the FOSSIstanbul conference. The conference was in March and right at the time when (travel) restrictions came into force step-by-step and news and government guidance changed roughly every minute. Thank you Frank for all the planning and replanning, and for deeply caring for both the conference and all its attendees.
We as FOSSi Foundation are also thankful for our sponsors, who help us cover administrative costs. If you or your company would also like to support the non-for-profit FOSSi Foundation reach out to us at email@example.com.
-The FOSSi Foundation Board of Directors
CHIPS Alliance, RISC-V International Partner for Open-Source Unified Memory Bus
The CHIPS Alliance has announced a partnership with RISC-V International to develop and launch a new open-source, standardised unified memory coherency bus based around OmniXtend, a cache-coherency protocol designed to export TileLink messages over L2 Ethernet frames.
“As RISC-V is increasingly being considered for high end data center and enterprise applications, there is a need for seamless cache-coherent sharing memory systems,” claims Dr. Zvonimir Bandić, Chairman, CHIPS Alliance, and senior director of next-generation platforms architecture at Western Digital. “CHIPS Alliance is cooperating with RISC-V to standardize on a unified memory fabric and leverage OmniXtend, which allows heterogenous systems that use TileLink cache-coherence protocol to share the memory coherently.
“We see a unique opportunity because RISC-V is freely open, while other architectures don’t open up the coherency bus, with RISC-V we can create an open unified memory standard to accelerate innovation for data-centric, heterogeneous applications.”
“ISAs do not stand alone. RISC-V needs a robust ecosystem,” adds RISC-V International chief technical officer Mark Himelstein, “and the OmniXtend roadmap will enable RISC-V members to create systems that deliver coherent, robust and performant solutions spanning the memory and storage hierarchies.”
Details of the new standard were presented in two sessions at the RISC-V Summit in December 2020, OmniXtend: Open Source Cache-coherence over Ethernet and Building Cache-Coherent Scaleout Systems with OmniXtend. OmniXtend itself is available on GitHub under the permissive Apache 2.0 licence.
OpenTitan Celebrates its First Anniversary
The OpenTitan project, a collaboration between Google, lowRISC, ETH Zurich, G+D Mobile Security, Nuvoton, Western Digital, and Seagate to produce the world’s first open-source silicon root-of-trust, celebrates its first anniversary this year — and has already hit a number of major milestones.
“During the past year, OpenTitan has grown tremendously as an open source project and is on track to provide transparent, trustworthy, and cost-free security to the broader silicon ecosystem,” says Google Cloud’s Dominic Rizzo, OpenTitan lead. “OpenTitan, the industry’s first open source silicon root of trust, has rapidly increased engineering contributions, added critical new partners, selected our first tapeout target, and published a comprehensive logical security model for the OpenTitan silicon, among other accomplishments.
“OpenTitan’s future is bright, and as a project it fully demonstrates the potential for open source design to enable collaboration across disparate, geographically far flung teams and organizations, to enhance security through transparency, and enable innovation in the open. We could not do this without our committed project partners and supporters, to whom we owe all this progress.”
A key announcement made during the celebrations was a collaboration between Google and Nuvoton to create the first silicon implementation of OpenTitan — the first time the concept will have been proven outside of FPGA implementations. Other milestones include the publication of a security model and the joining of 52 new contributors — bringing the total number working on the project to 100.
More details are available on the Google Open Source blog post.
Matt Venn’s Zero to ASIC Workshop Walks Through Using the Skywater PDK
Matt Venn has released a workshop, as part of the Hackaday Remoticon 2020 convention, demonstration how to use the Skywater Process Design Kit (PDK) to build your own custom silicon — and, thanks to Skywater’s partnership with Google, the resulting design can be taped out and produced free of charge for open-source projects.
“Matt Venn demonstrates how to go from zero to ASIC during this workshop held live during the 2020 Hackaday Remoticon,” the site writes in summary of the event. “It gives you a good overview and basic grasp of the terminology and processes involved.
“The demo shows the current capabilities of the Open Source tools and the Open Google/Skywater Process Design Kit (PDK) and free ASIC service (shuttle). Start from a simple digital design on paper and follow the process used to create the pattern files needed by the factory to build the ASIC. Synthesis of the hardware description language into basic digital building blocks like NAND gates and flip-flops.”
Matt has confirmed plans to launch a longer, more in-depth course under the same name, details of which are being posted to the Zero to ASIC website. The Remoticon version, meanwhile, is available on YouTube now, with a write-up on Hackaday.
Julian Stecklina Discusses Developing an OS for RISC-V on the ULX3S
Developer Julian Stecklina is working on the development of an operating system for RISC-V, using the Radiona ULX3S FPGA development board as a target platform — and has walked through his reasons for picking the two.
“Long story short: everything is simpler on RISC-V compared to x86,” Julian explains. “Seasoned x86 veterans may enjoy the Page Fault Weird Machine as a case in point. Given that my goal is to stay as low complexity as possible, the choice was easy.
“Since I wrote about RISC-V Stumbling Blocks, the hardware availability situation has notably improved. The different emulators are not the only choice for development any more. The ULX3S allowed me to experiment with different RISC-V SOCs, such as LiteX and SaxonSoc. SaxonSoc has excellent support for the ULX3S and supports everything from HDMI to audio output. The ULX3S community was extremely helpful in getting me going.”
“The whole workflow has a turnaround time of few seconds from editing code to running the binary on hardware,” Julian adds, “and I’m pretty happy with it. I haven’t covered how I actually build these ELF files, but this will be a topic for a future blog post.”
The full write-up, along with earlier posts on the same topic, can be fuond on Julian’s blog x86.lol.
More Kids Graduate Steve Hoover’s Popular RISC-V Workshop
Steve Hoover’s RISC-V workshop, in which attendees work towards designing their own pipelined processor core based on the RISC-V instruction set architecture, is proving popular with a surprising demographic: schoolkids.
“Last month I had the great pleasure of sharing a blog post about Nicholas Sharkey, an amazing 13 year-old who participated with graduate students and professionals in an online workshop of mine and developed his own pipelined RISC-V CPU core,” Steve explains, “an amazing feat for an 8th grader!
“I kinda feared when I posted about Nicholas that folks might get the wrong idea about the workshop. In fact, we had a second 12-year-old in this recent workshop as well. Yikes! These two 12-year-olds were less active in the chat than Nicholas had been, and I figured they would quietly drop off–and that would be for the best. But Niel [Josiah] checked in a few times with the mentors and kept at it, and, shortly after the official close of the workshop [Niel announced his successful completion.]”
The other 12-year-old attendee didn’t quite make it as far, but did successfully create a calculator circuit and expressed an interest in saving the more complicated parts of the course for later — “which,” Steve notes, “I’d consider a success in itself.”
Steve’s write-up is available on the RISC-V blog, along with links to the MYTH workshop — which, he notes, “is not designed for middle schoolers, [who should] grow up at their own pace.”
Antmicro Releases Reduced Pin Count (RPC) DRAM Support in LiteDRAM
Antmicro has released support for reduced pin-count (RPC) dynamic RAM (DRAM) in the latest update to its LiteDRAM, its open-source memory controller — in the hopes it will encourage its use in space-constrained projects.
“The Internet of Things is one of the areas that is hugely benefiting from miniaturization of semiconductor technologies, as more computing power can be encapsulated into increasingly smaller devices,” the company explains. “Shrinking in size and requiring less power, various devices — including AI-capable ones — are applied in ways that were not possible a few years ago.
“One of the new and exciting developments in this space is the emergence of RPC (reduced pin-count) DRAM — a small form factor memory, for which Antmicro has developed support in the open source memory controller, LiteDRAM. Our contribution, already made available on GitHub is being polished and undergoing final tests, and will be mainlined shortly.
“By creating support for RPC DRAM in LiteDRAM we have enabled the miniscule memory to be added to products that we build and to the whole LiteX ecosystem. This enables our customer’s devices to run more compute-hungry applications or full-fledged operating systems such as Linux in dedicated SoCs created by Antmicro on demand.”
The company’s full post is available on the Antmicro bog, while the RPC DRAM-enabled LiteDRAM release is available as a branch on GitHub under a custom permissive licence pending its merging into main.
PLCT Lab Releases First Minimal Android System for RISC-V
PLCT Lab’s Chen Wang has announced the release of a working, though extremely minimal, port of the Android Open Source Project (AOSP) mobile platform to RISC-V — successfully booting into a shell.
“The full name of our project is ‘AOSP for RISC-V,’” writes Chen by way of introduction. “The ultimate goal of our project is to port Android on RISC-V. Of course, this goal is huge. But in the short term, we still have a small goal, which is described in one sentence: based on the RISC-V platform, realise the kernel part of Android running on QEMU, and run the Android Shell.
“After some work, the above small goal has been initially completed, and at least one of the ‘minimal Android systems’ we defined above can be launched on QEMU. The related porting and modification have been opened on GitHub. […] You are welcomed to have a try and test, submit PR, or directly participate in our AOSP porting work.”
The initial port takes the form of a ‘toybox’ root file system with the mksh shell and an init system, the Bionic C library, and the Linux kernel with the Android 10 patch set, which can be booted on an emulated 64-bit RISC-V core via QEMU.
Full details, including a step-by-step setup guide, can be found on the PLCT Lab website. The source code, meanwhile, is available on GitHub.
European Processor Initiative Enters its Third Year with an Updated Roadmap
The European Processor Initiative, which aims to bring “independence in HPC [High-Performance Compute] technologies” to Europe, has completed its second year of operation — and enters its third with an updated roadmap that sees its RISC-V-based Rhea chips launched in 2022.
“European Processor Initiative partners have finalised the first version of our RISC-V accelerator architecture, named EPAC, and we look forward to the delivery of the first European Processor Initiative silicon featuring EPAC Test Chip in the exciting year that follows,” the organisation writes in a retrospective on 2020. “The EPAC Test Chip silicon will be complemented with PCIe EPAC Test Platform enabling the test and enhancements of the architecture for future revisions.
“At the software level, we already have a compiler supporting RISC-V vector intrinsics and automatic parallelization of C/C++ codes. We are evaluating the generated code on emulation platforms that provide detailed insight for the holistic co-design of applications, compiler, and architecture. We also have other software development vehicles (SDV) where we are adapting the Operating System for the Heterogeneous ARM+RISC-V architecture of the European Processor Initiative project.”
The full update is available on the EPI website.
New Paper Compares Scalar AES Instruction Set Extensions for RISC-V
A new paper published by researchers at the University of Bristol, in partnership with Microchip Technology, PQShield, and Symbiotic EDA, offers a look at the design of scalar instruction set extensions designed to accelerate AES cryptographic operations on RISC-V cores.
“Secure, efficient execution of AES is an essential requirement on most computing platforms,” the researchers, including first author Ben Marshall, write in the paper’s abstract. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose.
“RISC-V is a (relatively) new ISA that lacks such a standardised ISE. We survey the state-of-the-art industrial and academic ISEs for AES, implement and evaluate five different ISEs, one of which is novel. We recommend separate ISEs for 32 and 64-bit base architectures, with measured performance improvements for an AES-128 block encryption of 4x and 10x with a hardware cost of 1.1K and 8.2K gates respectively, when compared to a software-only implementation based on use of T-tables. We also explore how the proposed standard bit-manipulation extension to RISC-V can be harnessed for efficient implementation of AES-GCM.”
The paper has been published by the International Association for Cryptologic Research under a Creative Commons licence.
Michael Johnson Details an Experimental, Open-Source Memristor
Inventor Michael E. Johnson has published an article detailing an experimental open-source implementation of a memristor, or “memory resistor,” as a means of pushing the state of the art in open source hardware beyond the more common electronic components.
“I believe I may have a functional design for a memristor that lowers resistance with current, and would like others to attempt my experiment (and improve on it),” Michael writes, “with the goal of ultimately creating a simple device, much like a resistor, that can be used in DIY/maker circuits.
“I’m going to call mine an ‘electrolytic memristor’ — as it’s based on a NaSO4/Deep Eutectic electrolyte, and aluminium’s passivation properties. It also appears to have an interesting ‘diode’-like behaviour when operating.”
While Johnson’s proposed memristor component is a long way from being implementable inside a silicon chip, being produced by hand on a sheet of Tyvek using Kapton tape and an electrolytic solvent, so was the first transistor — and research has been ongoing for the electronic uses of a true memristor component since the concept’s first disclosure in 1971 by Leon Chua.
Michael’s full article is available on Medium.
FOSSi News In Brief
- De-RISC, aiming RISC-V at aerospace, celebrates its first anniversary and looks ahead to its second year.
- Hackaday: “A Xilinx Zynq Linux FPGA Board for Under $20? The Windfall of Decommissioned Crypto Mining.”
- Seagate follows Western Digital into developing in-house RISC-V cores for its storage product portfolio.
- Palmer Dabbelt: “RISC-V Patches for the [Linux] 5.11 Merge Window.”
- Imperas extends the riscOVPsimPlus simulator with configurable instruction trace, GDB/Eclipse support, and more.
- OpenPOWER Foundation: “OpenPOWER in 2020: A Year in Review.”
- OpenCAPI Consortium releases additional specifications, leverages IBM’s Open Memory Interface (OMI) reference designs.
- RISC-V International: “Another Strong Year of Growth with New Technical Milestones, Educational Programmes, RISC-V Adoption and More.”
- OneSpin boasts of OpenHW ecosystem contribution with automated formal solution for the CORE-V CVE4 RISC-V cores.
- Semiconductor Engineering: “Open Source vs. Commercial RISC-V Licensing Models.”
- Erik Engheim: “The Genius of RISC-V Microprocessors.”
- ZDNet: “The Open-Source RISC-V is Prompting Chip Technology Breakthroughs” (Video).
- Phoronix: “OpenBLAS 0.3.13 Released with a RISC-V Port, POWER10 Optimisations.”
- Intel announces “Open FPGA Stack”, promises it will be “source accessible.”
- ArchiTechnologia: “Olof Kindgren: Exclusive Interview for AT.”
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