El Correo Libre Issue 37

Published in

LibreCores

12 min readApr 13, 2021

Become a GSoC Student with FOSSi Foundation in 2021!

We are delighted to announce that we have once again been selected as a mentor organisation for the 2021 edition of Google Summer of Code (GSoC) Google Summer of Code is an excellent program for students to receive a stipend (generously provided by Google) to contribute to open source projects in the FOSSi community. As an organisation, we serve as an umbrella org for projects in the space of open source silicon design, EDA tools, and the surrounding ecosystem.

For those previously familiar with the program, please note that this year, there was a significant change. Google have changed the total expected length of the program from 350 hours to 175 hours and changed the coding period to span 10 weeks rather than 12. Further, eligibility has been expanded and so we hope to welcome new contributors to the FOSSi community as GSoC mentees.

To act as a first point of reference, we have prepared a list of project ideas. As a student you are free to base your project on one of these ideas, but remember that it is your idea we are looking for, and you should come up with an idea that you want to work on. Your job is to write a realistic project proposal (of appropriate scope) to show us that you have a good idea of the work involved, and discuss the idea with us to get feedback. Our job is to match you up with a suitable mentor.

As there are more student proposals than the number of slots we are likely to receive, a well-written project idea is important for us to judge your potential success as a FOSSi GSoC mentee. It is also a good idea to get involved with the community early on (perhaps via our gitter to get a better feeling for what kind of project you want to do, and what already exists. For more general information about what it takes to be a GSoC student, there are several guides available on the GSoC site, for example here

Please get in touch with the project maintainers from the list of ideas or with other projects you like. We are happy to answer questions about the program and the application procedure at gsoc@fossi-foundation.org.

Please also get in touch if you have project ideas with your community and think that FOSSi Foundation is the right umbrella organization for you!

You may also like to check out the following related GSoC orgs:

-Jonathan Balkind, Director, FOSSi Foundation

Antmicro Launches LPDDR4 Test Board, Adds PHY to LiteDRAM

Antmicro has announced the design and release of an open hardware test board, built around the Xilinx Kintex-7 FPGA, for LPDDR4 work — in support of its submission of an LPDDR4 PHY to Enjoy Digital’s LiteDRAM project.

“This [adds] support for LPDDR4 PHYs in LiteDRAM,” Antmicro’s Jędrzej Boczar writes in the pull request to the LiteDRAM project, which was founded to offer a small-footprint and configurable dynamic RAM (DRAM) core for open hardware projects. “[The] base PHY’s job is to convert DFI commands to LPDDR4 commands format and provide signals that are ready to be serialised using hardware blocks in a concrete PHY.”

Submitted in December 2020, the LiteDRAM LPDDR4 PHY has been under review — and has now been officially accepted into LiteDRAM. “[It’s] really nice to see that you’ve been able to add the LPDDR4 PHY support with very minimal changes to the Core itself, which shows that the current decoupling between the Core and PHYs is not that bad,” the company explains of its pleasure with the submission. “Adding support for new devices or new PHYs is generally a way to identify the limitations on the Core or on the decoupling.”

Antmicro’s open hardware test board, meanwhile, uses a Xilinx Kintex-7 FPGA with a custom DDR4 SODIMM connector, HDMI video output, gigabit Ethernet, micro-USB and JTAG debug, a microSD slot for storage, 16MB of QSPI flash, and an S27KL0641 HyperRAM chip.

More information on the LiteDRAM pull request can be found on Enjoy Digital’s GitHub repository, while Antmicro’s GitHub repository carries the test board design under a permissive Apache 2.0 licence.

Cocotb 1.5.1 Test Bench Package Brings New Features, Improved Stability

Cocotb, the coroutine-based cosimulation test bench environment for verifying VHDL and Verilog RTL with Python, has released release 1.5.1 — and brings with it some great improvements over previous releases.

“This release concludes a nine month development period,” FOSSi Foundation director Philipp Wagner explains, “slightly longer than the last releases. A major focus of this release was stability and ease of use (again), with some nice new features thrown in.”

Among those new features are assertion rewriting, in which assertion failures will bring in the actual value read from the simulation alongside the expected value as a means to speed debugging, support for building extension libraries with Microsoft Visual Studio C++, and improved documentation.

“After this 1.5 release we’ll take the opportunity to say goodbye to some quirks in cocotb,” Philipp continues. “We will be looking at the way signal values are represented in cocotb (the BinaryValue class) and solve some long-standing issues there. We also plan to look at some of cocotb’s scheduling behaviour and try to align it more with what users of recent approaches such as asyncio have come to expect. Surgery of this kind isn’t possible in a fully backwards-compatible way, and that’s why we’ll release the next version as cocotb 2.0.”

The full release notes are available on cocotb’s documents portal, while the latest release can be found on GitHub under the permissive Revised BSD Licence.

Open Source FPGA Foundation Aims to “Democratise and Promote”

The newly-formed Open Source FPGA Foundation has launched with a stated aim of promoting the cause of open-source technologies in the field programmable gate array (FPGA) industry.

“The Open Source FPGA Foundation will serve to enhance the spectrum of innovation for FPGAs globally,” claims Dr. Naveed Sherwani, Foundation co-chair and co-founder. “There is a very strong demand for more flexible designs, open source tools and methodology will allow for much greater innovation in the FPGA design space. We thank all our partners for their strong support of our launch and look forward to working with our members to drive the true democratization of FPGA technology.”

Founding members feature representation from both academia and industry including the Universities of Utah and Toronto, Quicklogic, Zero ASIC, the École polytechnique fédérale de Lausanne (EPFL) and GSG Group. The Foundation is to be led by chief executive Dr. Shrikant Lohokare.

“[The OSFPGA Foundation aims] to set FPGA companies free from engineering-labour intensive process in producing FPGA chips, give full freedom for software developers when customise FPGA software stacks and provide an open collaboration for FPGA end-users to implement high-quality designs,” its founders state.

More information can be found on the official OSFPGA Foundation website.

Chips4Makers’ PDKMaster Hits v0.1 Release, Gains FreePDK45 Example

Staf Verhaegen has announced a milestone release in the PDKMaster project, which aims to create a PDK management tool and design and layout framework for ASIC design.

“After a lot of blood, sweat and tears,” Staf writes, “I have now reached a new milestone for my NGI0 NLnet project. I released v0.1 of the PDKMaster python framework together with a standard cell library generator and an example PDK implementation for the FreePDK45 technology.”

The PDKMaster v0.1 release offers Python classes for primitive descriptions, classes for circuit and layout representation plus design-rule checking, “effortless scalability” between production node technologies, export functionality, and a simulation interface.

At the same time, Staf has released an example based on the FreePDK45 open-source design kit, demonstrating its implementation in PDKMaster. “The FreePDK45 technology description is mainly one Python file,” Staf explains, “from which everything else is generated.”

More details on the releases, and a scalable standard cell library to go with them, can be found on the Chips4Makers website.

RI5CY Core, XpulpV2 Extensions Add “Top-Notch” Autonomy to a Nano-Drone

The Parallel Ultra-Low Power (PULP) Platform was the focus of a recent academic paper demonstrating how the RISC-V-based low-power technology can be used to add autonomous flight capabilities to an off-the-shelf “nano-drone” without weighing it down.

The paper focused on the tiny Crazyflie 2.1 nano-drone, and worked to add a deep neural network (DNN) with computer vision and flight control capabilities to the device despite its extreme size and weight constraints. The solution: The free and open-source RI5CY core, extended with the XpulpV2 instructions to improve performance for edge-AI tasks and using it to run a custom convolutional neural network dubbed PULP-Frontnet.

“Our work stands at the intersection of the novel parallel ultra-low-power (PULP) architectural paradigm and our general development methodology for deep neural network (DNN) visual pipelines, i.e., covering from perception to control,” the researchers write in the paper’s abstract. “Solving this HDI [human-drone interaction] problem on an autonomous nano-drone is a challenging and valuable task in the IoT domain. These robotic helpers can be envisioned as the next-generation ubiquitous IoT devices, ideal for indoor operations near humans.”

Running on the GreenWaves Technologies GAP8, a commercial implementation of the PULP Platform’s efforts, the PULP-Frontnet CNN was able to run at up to 135 frames per second while drawing 86mW and requiring just 184kB of memory.

The paper has been published under open-access terms on arXiv.org.

PULP Platform Releases Ara, a 64-Bit RISC-V Vector Coprocessor for CORE-V Ariane

The Parallel Ultra-Low Power (PULP) Platform has officially launched Ara, a vector machine coprocessor designed for use with its CVA6 Ariane core — despite project co-founder Luca Benini having previously dismissed the possibility of the project extending to a vector processor.

“Never say never,” the PULP Project team writes in a Twitter announcement of the project. “It is with great pleasure that we are announcing the release of Ara, PULP’s Vector Machine. Ara is a co-processor to Ariane (CVA6), with support to the v0.9 of the RISC-V Vector Extension.”

First introduced in a paper written by Matheus Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, and Luca Benini for the journal IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Ara has been implemented on GlobalFoundries’ 22FDX process and offers performance up to 33 DP-GFLOPS at 1GHz.

More information on the technology behind Ara is available in the team’s paper, while Ara itself has been released under the permissive Solderpad Hardware Licence on the PULP Platform GitHub repository.

Will Green Releases FPGA Framebuffer with Async Read/Write

Developer Will Green has released released an FPGA framebuffer, under his Project F, which aims to be easy to use yet offer the ability to run designs divorced from the speed of the pixel clock.

“I’m rolling out my new #FPGA framebuffer,” Will explains in the Twitter announcement. “It’s simple to use, yet supports asynchronous read/write, so you’re not limited to running your designs at pixel clock.

“The Verilog designs are open source under the MIT licence. I also include an iCEBreaker makefile for Yosys/nextpnr and Xilinx Vivado project script.”

The framebuffer is designed to be part of the Project F educational blog post series, and comes with its own entry in the blog: Lines and Triangles. It also makes use of existing Project F common modules, all of which are made available under the same permissive MIT licence.

The source code for the framebuffer is available now on Will’s GitHub repository.

Ben Newhouse Puts a Bluetooth Receiver on his Xilinx FPGA via Nmigen

Developer Ben Newhouse has demonstrated a Bluetooth receiver working on a Xilinx FPGA, written in nmigen and requiring only 1.5k LUTs — and he’s going to release the source code soon.

“I just built a Bluetooth receiver using nothing but a Xilinx FPGA and an antenna,” Ben announced of the project via Twitter. “No ADC, no filters, no mixers, no AGC, not even an amplifier. Just straight RF into a SERDES port at 5 GHz. It’s not a great receiver, but I’m stunned it works well enough to discover my neighbor’s TV!

“Written in nmigen, uses ~1.5k LUTs w/ no DSPs (and no CORDIC, fwiw). Packet checking and printing is done in pure hardware because I didn’t want to fit a CPU in my dev feedback loop. This radio has in-excess of 2.5 GHz of simultaneous bandwidth! I could very easily duplicate my digital logic for every Bluetooth channel and simultaneously listen on every channel at once.”

Additional details on the project have been released on Ben’s Twitter, though the source code is not yet publicly available. “Once I tidy things up and figure out the right OSS licence,” Ben explains, “[I’m] aiming to push the code for this to GitHub too.”

Carlos Eduardo Demonstrates a “Full Open Source FPGA Stack” — Almost

Carlos Eduardo has shown off a project representing a full open source FPGA stack, bar the underlying processor powering the development system — though that, too, may follow in time.

“That’s it,” Carlos announced on Twitter, “a full open source FPGA stack from Yosys generating SERV, a RISC_V core by Olof Kindgren, on a RISC-V host, the SiFive Unmatched. CoreScore was 100% built and programmed into [a] Radiona ULX3S FPGA in RISC-V! Open source to the core!”

While the RISC-V instruction set architecture itself is free and open, however, Carlos later clarifies: “The U74 core used on the Unmatched board has not [been] open sourced by SiFive (yet?). The U54 that is used on the Unleashed board is open source as the Rocket Chip.”

The process of building the system with FuseSoC took around five minutes, using two of the SiFive Unmatched’s RISC-V cores. “[The] main issue,” Carlos explains, “is that all tools are single-threaded.”

More details are available in the project’s Twitter thread.

Edalize Python Library Gains Support for Containerised Tools

The Edalize Python library, designed to ease interaction with a range of electronic design automation tools, has gained a significant new ability: support for handling containerised tools.

“Edalize now supports using containerized EDA tools,” project maintainer and FOSSi Foundation director Olof Kindgren explains via Twitter. “Thanks to Carlos Eduardo for kicking this off. Best of all, the Dockerized tools made SERV 3FF smaller.”

To demonstrate the new capability, Olof published a quick-start guide in which the user is walked through installing FuseSoC, creating a new workspace, adding SERV as a FuseSoC library, downloading and executing the Docker launcher, and finally running FuseSoC via the downloaded launcher. Additional documentation will follow, Olof promises.

Additional details are available from Olof’s Twitter thread.