El Correo Libre Issue 4
Reports from the RISC-V Barcelona Workshop 2018
Welcome to the June issue of El Correo Libre, the official newsletter of LibreCores and the Free and Open Source Silicon Foundation. There’s no better place to start things off, of course, than to take a look at the eighth RISC-V Workshop which recently took place in Barcelona — and there was plenty for attendees to see and do, including welcome news from the RISC-V Foundation’s Rick O’Connor that the Foundation has grown to over 150 members distributed across 25 nations of the world.
The official event recap published by the Foundation reports 325 attendees, making it the biggest event it has ever held outside Silicon Valley, “demonstrating the momentum of the RISC-V Foundation and the growth of the ecosystem in Europe.”
UltraSoC chief executive Rupert Baines tells of his experience at the event for Embedded Computing Design, however, and highlights a surprising lack of locals: “While North American and Asian companies turned out in force, the geographical area that was worst represented was Europe — even more surprising given the venue,” he writes. “It worries me that, with a lack of European firms in the vanguard, RISC-V might prove to be yet another technology where Europe has missed out by getting involved too late.”
Alex Bradbury of the lowRISC project, meanwhile, has a more complete write-up the event’s presenters split into day one and day two live blogs. These bullet lists of topics go well with the slides and other materials since published to the Foundation’s proceedings page.
The next RISC-V Workshop is scheduled to take place at the Indian Institute of Technology Madras in Chennai on July 18th and July 19th 2018. The call for participation is open until June 15th 2018.
Joe Fitz Updates WTFpga Open-Source Crash Course
Those just starting to experiment with field-programmable gate arrays (FPGAs) may benefit from a newly updated, open-source Verilog-based beginner’s course from Joe Fitz dubbed WTFpga.
“The purpose of this workshop is to jumpstart people new to FPGAs, getting them to the point where they can understand and make minor changes to Verilog designs, and see the results on hardware,” Joe explains of the project. “When delivered as a workshop, laptops have Vivado preinstalled and the project preloaded so that attendees can get straight to toggling switches and flashing LEDs.
“The scope is intentionally limited to make sure it’s doable in a couple hours time, so that attendees don’t need to make a huge time commitment to get a hands-on understanding of FPGAs and Verilog.”
The course is based around a Digilent Basys 3 board and Xilinx Vivado, building on work Joe did in 2014 on a similar course using the Xilinx XC3S200A FPGA, and is published under a the GNU General Public Licence v2.
The full course can be found on Joe’s GitHub repository.
Optimised EDGE Microarchitecture Brings Efficient Out-of-Order Execution to FPGAs
Jan Gray and Aaron Smith have jointly published a paper, Towards an Area-Efficient Implementation of a High ILP EDGE Soft Processor, which introduces a new out-of-order execution (OOOE) microarchitecture based on the Explicit Data Graph Execution (EDGE) instruction set architecture.
“In-order scalar RISC architectures have been the dominant paradigm in FPGA soft processor design for twenty years,” the pair explain in the paper’s abstract. “Prior out-of-order superscalar implementations have not exhibited competitive area or absolute performance.
“This paper describes a new way to build fast and area-efficient out-of-order superscalar soft processors by utilizing an Explicit Data Graph Execution (EDGE) instruction set architecture. By carefully mapping the EDGE microarchitecture, and in particular, its dataflow instruction scheduler, we demonstrate the feasibility of an out-of-order FPGA architecture.
“In the context of commercial 200MHz, 1,000–2,000 LUT soft processors, the limited FPGA resource cost and clock period impact of either design seems acceptable and practical. Both design alternatives will scale well to future four-decode/two-issue implementations.”
The paper is available to view now under open access on arXiv.org.
Greg Davill Releases Boson Thermal Camera Driver Board, Core
Engineer Greg Davill has designed an FPGA core and hardware driver board for the FLIR Boson thermal camera core, designed to capture the data stream and transfer it into a usable format.
“This is my very first FPGA project,” Greg explains in a blog post introducing the first hardware revision. “I had used FPGAs before in a uni class on Digital Electronics. I had also learnt about the RISC-V CPU architecture in Computer Architecture. But had never designed an FPGA into a project. I had just listened to an episode of the Amp Hour with Clifford Wolf, explaining the Lattice iCE40 open source toolchain: icestorm. So naturally I started there. (Also naturally I picked the only variant in the iCE40 family that is not compatible with icestom. Still supported by Lattices’ tools.)
“I designed the FPGA to be configured through a slave device of the [Atmel AT] samd51. This took too long to get working, by the time I had it working and had started working on the verilog the new prototype had arrived, and I decide to leave this project. It had served as a great first step in getting started with FPGAs and had given me added confidence with the tools and workflow.”
A redesign, detailed in full on Greg’s blog, resulted in a board barely larger than the camera module itself with the FPGA core handling most tasks. More information, and the hardware and software design files which are published under the permissive MIT Licence, are available on the project’s GitHub repository.
Project Trellis Lattice ECP5 Architecture Documentation Efforts Reach Milestone
Project Icestorm contributor David Shah has been writing of his efforts on documenting the architecture of the Lattice ECP5, including the recent publication of documentation for all logic tile multiplexor bits and a first hardware test.
“Successfully documented all routing mux bits of the ECP5 logic tile as part of #prjtrellis,” David writes on microblogging service Twitter. “I am reasonably happy that we now understand every bit used by Lattice Diamond in the ECP5 logic tile in #prjtrellis! Next steps: finish documenting LUT init and config bits. Then onto more tiles!”
David has also written of his efforts with a fuzzing infrastructure — “Netname normalisation, database manipulation and the base generic interconnect fuzzer seem to be working,” he explains — and in a breakthrough moment mid-May published a brief video of the project’s first hardware test.
More information on Project Trellis is available from the official documentation, while David’s efforts can be followed live via the Twitter hashtag #prjtrellis.
Project X-Ray Releases Xilinx Virtex 7-Series Bitstream Doc, Seeks Assistance
Clifford Wolf’s SymbiFlow has released a full and detailed analysis of the Xilinx Virtex 7-Series FPGA bitstream format, as part of Project X-Ray, and is seeking assistance with extending the project to include additional devices.
In a PDF published to the project’s documentation page, Clifford and colleagues detail the bitstream format of the low-cost Xilinx Virtex 7-Series FPGA, along with the tools used to discover said architecture, as the first step in the process of building a fully open development chain for the devices.
“For some context this is a very popular and cheap series of FPGA devices. For example you can buy the Arty board which has one of these FPGAs for $99, or the slightly more advanced Nexys 4 DDR for $265,” writes Richard Jones of the news in a blog post on the matter. “Currently you must use the Xilinx Vivado tool which is a 40 GB download [no, that isn’t a typo], requires a paid licence to unlock the full features, and is generally awful to use. This work should eventually lead to a complete open source toolchain to program these devices, just like Project IceStore for the Lattice devices.”
Project X-Ray, which is now seeking volunteers to document additional devices, can be tracked on its GitHub Repository or official documentation.
Andrew ‘bunnie’ Huang Announces NeTV2 Open Development Board
Noted engineer Andrew ‘bunnie’ Huang has announced his latest project, an open video development board dubbed the NeTV2 and based on a Xilinx XC7A35T FPGA.
“As limited by the prevailing law, the NeTV2 can only process unencrypted video and perform encryption-only operations like video overlays through a trick I call ‘NeTV mode,’” bunnie explains in his project announcement. “However, it’s my hope this is a sufficient platform to stir the imagination of developers and users, so that together we can paint a vibrant picture of what a future looks like should we have the right to express our ideas using otherwise controlled paints on otherwise denied canvases.
“The heart of the NeTV2 is an FPGA-based video development board in a PCIe 2.0 x4 card form factor. The board supports up to two video inputs and two video outputs at 1080p60, coupled to a Xilinx XC7A35T FPGA, along with 512 MiB of DDR3 memory humming along at a peak bandwidth of 25.6 Gbps. It also features some nice touches for debugging including a JTAG/UART header made to plug directly into a Raspberry Pi, and a 10/100 Ethernet port wired directly to the FPGA for Etherbone support.
“For intrepid hackers, the reserved/JTAG pins on the PCI-express header are all wired to the FPGA, and microSD and USB headers are provisioned but not specifically supported in any mode. And of course, the entire PCB design is open source under the CERN OHL licence.”
More information on the device is available on the Crowd Supply campaign page, where board-only pledges begin at $200 (exc. taxes).
Arduino Announces MKR Vidor FPGA Development Board
Arduino, a name better associated with low-cost microcontroller and microprocessor development boards primarily aimed at the educational and hobbyist markets, has announced it is getting into the FPGA game with the impending launch of the MKR Vidor.
“The MKR Vidor 4000 is the first-ever Arduino based on an FPGA chip, equipped with a SAM D21 microcontroller, a u-blox Nina W102 WiFi module, and an ECC508 crypto chip for secure connection to local networks and the Internet,” the team confirms of the board’s design in a blog post. “[The] MKR Vidor 4000 is the latest addition to the MKR family, designed for a wide range of IoT applications, with its distinctive form factor and substantial computational power for high performance. The board will be coupled with an innovative development environment, which aims to democratise and radically simplify access to the world of FPGAs.”
The on-board FPGA includes 16,000 logic elements, 504kb of embedded RAM, and 56 18x18 hardware multipliers. More details on the board, not including yet-to-be-disclosed pricing, is available on the Arduino Store.
Parallel Programming for FPGAs Targets High-Level Synthesis Students
The latest revision of educational title Parallel Programming for FPGAs has been released under the permissive Creative Commons Attribution 4.0 International Licence, and its authors — Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer — are seeking volunteers to help improve it even further.
“We noticed a lack of material aimed at teaching people to effectively use HLS tools,” the authors explain on the project’s homepage. “The book was developed over many years to serve as a primary reference for UCSD CSE 237C — a hardware design class targeting first-year graduate students and advanced undergraduate students. We hope that you find it useful for learning more about HLS, FPGAs, and system-on-chip design. We encourage you to make edits, add material, and fix errors.”
Those interested in reading more about the book can find a write-up on Hackaday, or simply download the latest release in PDF format from the project homepage; anyone wishing to help improve the book, meanwhile, can find the source on the project’s GitHub repository. The book is also available via arXiv.org.
Luke Gorrie Announces EasyNIC Open Network Interface Project
Developer Luke Gorrie has begun work on a project to create a friendly and open host interface for network cards, inspired by the increasing interest in the RISC-V open instruction set architecture.
“EasyNIC is the specification of a hacker-friendly interface between a computer and a network interface card (NIC),” Luke explains on the project’s GitHub repository. “Design goals: Make device driver development easy; Provide a minimal ‘high-speed serial port’ operating mode; Support 100G and beyond (use PCIe bandwidth efficiently); Support optional extensions (in later versions). EasyNIC is inspired by the success of RISC-V.”
Luke has asked interested parties to share any ideas they have for the EasyNIC project on the GitHub repository’s Issues page, with suggestions so far including conservation of PCI Express bandwidth, efficient support of multiple read and write cores, and a benchmark for validating the design.
Richard Brewster Recreates the First Flip-Flop Circuit, 100 Years On
Richard Brewster has written of his effort to recreate the original flip-flop circuit design, as part of its centennial celebration — and he stuck as closely as possible to the original design, including the use of a pair of vacuum tubes.
“Few know the names of William Eccles and F.W. Jordan, who applied for a patent for the flip-flop 100 years ago, in June 1918,” Richard writes of his inspiration. “The flip-flop is a crucial building block of digital circuits: It acts as an electronic toggle switch that can be set to stay on or off even after an initial electrical control signal has ceased. This allows circuits to remember and synchronise their states, and thus allows them to perform sequential logic.
“With a lot of trial and error and tweaking of my nearly century-old components, over the course of a year I was finally able to achieve stable operation of this venerable circuit!”
Richard’s full project write-up is available on the IEEE Spectrum website.
Kevin Hubbard Launches SUMP2 and DeepSump Challenge
Electrical engineer Kevin Hubbard has launched a challenge for fellow FPGA enthusiasts: port and demonstrate the SUMP2 open source hardware logic analyser and DeepSump extension on a new platform.
“Soliciting (challenging) anyone with a FPGA dev board with an external memory and a FTDI-like serial interface to port and demonstrate SUMP2+DeepSump on their platform,” Kevin writes on Twitter. “SUMP2+DeepSump work together as dual-screen experience. SUMP2 provides GUI for assigning triggers and viewing 32 events and up to 16 DWORDs (512 bits) near trigger event. DeepSump captures and exports VCD to GTKwave that provides a ‘big picture’ using 32 events RLE compressed.
“Real World example, 16 DWORDs capture to BRAM with 1uS of depth around trigger. 32 events captured to BRAM via RLE with 1mS of depth around trigger. DeepSump captures 10 Sec of depth around trigger using 32 events RLE compressed and stored to external DRAM. Regular SUMP2 falls apart using more than about 8Kx64 of Block RAM as sump2.py decompresses the RLE and renders samples which can easily consume 1–2 Gigabytes of CPU DRAM. With DeepSump RLE is converted direct to VCD 1:1 and GTKwave handles all the samples easily.”
Those interested in trying SUMP2 and the DeepSump add-on can find it on the Black Mesa Labs GitHub repository. Kevin has also teased a finished design for the Black Mesa Labs’ S7 Mini FPGA development board, which includes a Xilinx Spartan 7 &S25 and 64Mb of DRAM.
Using an Arduino as a Breadboard-Compatible Low-Cost ‘FPGA’
While the Arduino project may be positioning its new MKR Vidor 4000 development board as the first to include an FPGA, Instructables user JeremyW96 has approached things from a different angle: using a classic microcontroller-based Arduio Uno as an introduction to FPGA concepts.
“Designing hardware logic circuits can be fun. The old school way to do this was with NAND gates, on a breadboard, wired up with jumper wires,” Jeremy explains. “This is still possible, but it doesn’t take much before the number of gates gets out of hand.
“A newer option is to use an FPGA. These chips can rewire themselves to become any digital logic circuit you can design, but aren’t cheap and readily available. I will show how this FPGA can be replaced with a cheap Atmega chip from an Arduino UNO, effectively putting the digital circuit into a DIP package, which is very breadboard friendly.”
Jeremy’s tutorial walks through the creation of a 2-bit adder using three methods: beginning with 14 NAND gates across four quad-gate TTL chips, reimplementing the adder on a Lattice iCEstick FPGA development board, and finally replacing the FPGA board with the significantly cheaper Atmel ATmega-based Arduino Uno using a tool which accepts Verilog and outputs C++ code — allowing the design, with a little modification, to be compiled for and executed on the Arduino Uno.
“TTL chips work, but it takes a lot of them to build anything. FPGAs work really well, but aren’t cheap. If you can live with fewer IO pins, and lower speed, then an Atmega 328P may be the chip for you.”
Jeremy’s write-up can be found on Instructables.