El Correo Libre Issue 40

Published in

LibreCores

14 min readJul 13, 2021

Google Summer of Code (GSoC) Class of 2021

The FOSSi Foundation is happy to introduce our Google Summer of Code Class of 2021 projects. This year we are grateful that we have been granted eleven slots by Google to support projects and students. We are thankful for all mentors who volunteered to supervise students, and we’re looking forward to a great summer working together on Free and Open Source Silicon projects.

Virtual FPGA Lab (Bala Dhinesh)
Mentored by Kunal Ghosh, Ákos Hadnagy, and Steve Hoover
Bring up CV32E40P AI accelerator on FPGA (Veronia Iskandar)
Mentored by Jeremy Bennett and William Jones
WARP-V manycore in the Cloud (Vineet Jain)
Mentored by Ákos Hadnagy, Steve Hoover, and Shivam Potdar
M-extension support for SERV (Zeeshan Rafique)
Mentored by Olof Kindgren and Stefan Wallentowitz
FuseSoC Integration of BaseJump STL (Adithya Sunil)
Mentored by Olof Kindgren, Dan Petrisko, and Michael Taylor
TensorCore Extension for Deep Learning (Nitin Mishra)
Mentored by Steve Hoover and Theodore Omtzigt
Formal verification of mor1kx (Harshitha S)
Mentored by Stafford Horne and Stefan Wallentowitz
SkyParrot: Preparing BlackParrot for Open-Source Fabrication using Google-Skywater 130nm PDK (Lakshmi S)
Mentored by Dan Petrisko and Michael Taylor
Block-Based Circuit Design (Ninad Jangle)
Mentored by Steve Hoover, Gayatri Mehta, and Adam Ratzman
Parallelising Verilog RTL Simulations Using MPI (Guillem Lopez Paradis)
Mentored by Jonathan Balkind and Stefan Wallentowitz
Multi-Level TLB Support for Ariane Core (Nazerke Turtayeva)
Mentored by Nils Wistoff and Jonathan Balkind

These projects are our “GSoC Class of 2021.” Please give our students a warm welcome!

Full details on each of the above projects, which range from improving access to FPGA educational resources through the development of a simulation platform to adding M-extension support to the ultra-compact bit-serial SERV CPU, are available on the FOSSi Foundation blog.

-Jonathan Balkind, Director, FOSSI Foundation

Antmicro Showcases Co-simulation Updates with Renode and Verilator

Free and open-source silicon pioneer Antmicro has published an update on the co-simulation capabilities of Renode and Verilator, using the FastVDMA direct memory access controller running on the Microchip PolarFire SoC platform as a practical example.

“By co-simulation we mean a scenario where a part of the system is simulated in Renode but some specific peripheral or subsystem is simulated directly from HDL, e.g. Verilog,” the company explains. “To achieve this, Renode integrates with Verilator, a fast and popular open source HDL simulator, which we are helping our customers adopt as well as expanding its capabilities to cover new use cases. Peripherals simulated directly from HDL are typically called Verilated peripherals.

“Co-simulation is a highly effective approach to testing IP cores in complex scenarios. HDL simulation is typically much slower than functional simulation, so to cut down on development turnaround time you can partition your design into a fixed part that you can simulate fast using Renode and the IP you are developing that you can co-simulate using Verilator. Renode offers a lot of ready-to-use components — for which you do not need to have a hardware description — which can be put together to provide a complete system to test new IP core designs.”

While co-simulating with HDL was possible in Renode 1.7.1, the feature got a major upgrade in Renode 1.12 — including an expanded application programming interface (API) and support for the AXI4 bus. “The Verilated peripheral can either act on AXI4 bus as a controller that requests accesses (therefore utilising these new Renode API actions),” the company explains, “or as a peripheral (in the AXI4 bus context) that is only requested to take some action.”

The full post, including practical examples based around the FastVDMA controller, is available on the Antmicro website.

Sylvain Lefebvre Packs a Fully-Functional RISC-V CPU onto a T-Shirt — in Silice

Silice creator Sylvain Lefebvre has showcased just how efficient his language, designed specifically for working with field-programmable gate arrays, can be — by showing off a design that puts a completely-functional RISC-V CPU on the front of a T-shirt.

Inspired by classic code-based T-shirts of the past, including the infamously blocked-from-export-by-ITAR Perl RSA Dolphin, Sylvain’s T-shirt features just 160 lines of code.

“Silice Ice-V RISC-V CPU fits equally well on a T-shirt than in an IceStick FPGA board,” Sylvain writes of the project. “955 LUTs, validates ~65 MHz, 160 lines of code (300 commented, 80 cols). And if features a C demo code for a RISC-V DooM fire!

“Silice has improved a lot since a year ago when I developed the Ice-V, and I also learned quite a bit. I was able to easily save 200+ LUTs and increase frequency by 15+ MHz! But I was not alone! I borrowed a couple tricks from Bruno Levy’s FemtoRV, in particular using a single adder to perform all comparisons, as well as using a separate adder for address computations.”

The full source code, which measures 300 lines when you add the comments, is available with a walk-through of its design on the Silice GitHub repository under the GNU Affero General Public Licence 3; an image of the T-shirt has been published on Sylvain’s Twitter account.

Kactus2 Open-Source IP-XACT Toolset Hits 3.9.0, Gains Python API

Kactus2 3.9.0, the latest version of the open-source tool set for working with IP-XACT XML reusable circuit design files, is now available — and brings with it a brand-new Python-based application programming interface (API) for working with IP-XACT data.

“New PythonAPI for accessing Kactus2 data,” project maintainer Esko Pekkarinen writes in the changelog for the new release. “[It includes] new interfaces for IP-XACT data read and modify. Generator runs for selected generators e.g. Verilog”

The new API also comes with a Python console in the project’s graphical user interface, allowing for the execution of interactive scripts, command history display, and the saving and loading of script files for interfacing with the new API.

The new release also includes a number of bug fixes, modified editors which adapt to the project’s new interfaces, the option to extend port abstractions, a new dependency analysis feature for Verilog and SystemVerilog module instantiations, and a new plugin for CMSIS System View Description (SVD) generation from a hardware design.

The latest release, and its source code, is available on the project GitHub repository now under the GNU General Public Licence 2. Full details on the changes in v3.9.0 are available on the project management site.

OpenPOWER Foundation’s Announces Libre-SOC’s Impending Production on 180nm

The OpenPOWER Foundation has announced that the Libre-SOC project, in collaboration with Chips4Makers and Sorbonne Université’s LIP6, is heading to production at Taiwan Semiconductor (TSMC) on a 180nm node as part of the Imec MPW Shuttle Service.

“Implementing a fixed-point subset of the v3.0B OpenPOWER ISA, Libre-SOC’s 180nm Power ISA Test ASIC is the world’s first Power ISA implementation designed outside of IBM to go to silicon, following IBM’s open sourcing of the POWER ISA in 2019,” the Foundation explains. “Libre-SOC used Microwatt, which was designed by IBM and sent to SkyWater for fabrication earlier this year, as a reference design for benchmarking and cross-verification.

“The ASIC is 130,000 gates, measures 5.5 x 5.9 mm², contains four 4k SRAMs developed by Chips4Makers, and a 300 MHz Voltage-Controlled PLL developed by Professor Galayko of Sorbonne Université. The VLSI tape-out was carried out by Jean-Paul Chaput of Sorbonne Université using coriolis2, and the Static Timing Analysis and LVS checking by Dr. Marie-Minerve Louërat of Sorbonne Université. The HDL of the core is entirely in nmigen, a python Object-Orientated HDL.”

“We developed this ASIC on the Power architecture because of its supercomputing pedigree, and the decades-long commitment and stability that IBM and other OpenPOWER Foundation members have sustained,” says Luke Kenneth Casson Leighton, Libre-SOC’s lead developer and coordinator, of the project. “On this strong base, we can build a reliable, efficient Hybrid 3D CPU-VPU-GPU, and our next test ASIC will include Draft Cray-style Vector Extensions, SVP64.”

More details on the Libre-SOC project are available on the project website and in the Foundation’s blog post.

ICT CAS Targets High Performance with Free and Open XiangShan Cores

The Institute of Computing Technology at the Chinese Academy of Sciences (ICT CAS) is working on RISC-V-based processor designs targeting the upper end of the performance spectrum, aiming to go toe-to-toe with Arm’s proprietary Cortex-A76 cores — yet is releasing them under a permissive licence.

Currently in its second generation, with work underway on a third, the XiangShan — “Fragrant Hills” family of processor cores are out-of-order pipelined RISC-V implementations. The first generation, Yanqi Lake is an 11-stage, six-issue core taped out for production on TSMC’s 28nm node and targeting 1.3GHz with seven SPEC CPU 2006 points per gigahertz; the second-generation Nanhu Lake targets 2GHz on a 14nm node with 10 points per gigahertz.

While performance is already high, the group developing the cores is hoping for more. “The performance-to-power ratio of the [Arm Cortex-]A73 is very good, reaching a performance higher than that of the XiangShan processor under the width of the second launch [issue],” developer Yinan Xu writes in the project’s documentation. “The XiangShan is currently six [issues], so the efficiency of XiangShan is not as good as that of the [Cortex-]A73.

“Although our long-term goal in the future is to be in line with [Cortex-]A76, it is still in progress. We need down-to-earth iterative optimisation. The purpose of agile development is not to overtake a corner. The experience accumulated by Intel and Arm over the years, we also need to accumulate slowly.”

The project’s code, written in Chisel, has been published to GitHub under the permissive Mulan Permissive Software Licence 2 (MulanPSL2) — a Chinese licence equivalent to Apache 2.0.

InCore Semi, Tessolve Launch Open-Source RISC-V Verification Tool, RiVer

InCore Semi and Tessolve have jointly launched a Python-based, permissively-licensed verification tool dubbed RiVer, designed to offer a scalable framework for RISC-V processor verification work.

“Through the RiVer Core framework, you can continue to build and generate new tests using an existing environment and scripts independently of the environment chosen/used by the target or the reference,” InCore writes of the project. “Similarly, you can easily replace the reference models for different tests depending on the test’s requirements. Unlike other conventional frameworks, RiVer takes a more holistic approach and avoids creating any environment tailored to a specific test-suite, target environment or reference environment, thereby allowing use of RiVer in existing environments.”

The framework requires three components: A set of tests, which can be random or directed; a RISC-V target, which InCore says can be either an RTL implementation or “other micro-architecture models”; and a reference model to detect pass/fail conditions.

“What makes RiVer truly extensible,” the company continues, “is in its approach to keep the above 3 components completely independent and decoupled each other, thereby enabling any combination of test-suite , target and reference model to co-exist effortlessly. RiVer achieves this broad range extensibility via its plugin based approach. RiVer splits the entire flow into 3 major parts: Test Generation, Running Tests on the Target/DUT and Running Tests on the Reference Model and defines specific plugin APIs for each of these parts, thereby enabling easy and early verification bring-up.

“While InCore and Tessolve continue to enhance and maintain RiVer Core, we also invite constructive feedback and contributions to this effort in any form possible.”

The project source code has been published to GitHub under the permissive BSD 3-Clause licence.

RgGen Register RTL Generation Tool v0.25.3 Improves Plugin Support

The latest releases of RgGen, a tool for generating RTL code for configuration and status registers, bring with them improved support for a plugin architecture designed to vastly expand its compatibility with a variety of projects.

“RgGen supports the ‘plugin’ feature; this is to customise RgGen to your environment,” explains project maintainer Taichi Ishitani of the project’s latest releases. “You can make RgGen support your specific bit fields types and your own bus protocol by creating your own plugin. Also you can create your own input loader plugin and output write plugin too.”

To support use of the tool’s plugin architecture, Taichi has written a guide on the project wiki to showcase how to create a custom plugin with a new bit field type. The code for a sample plugin has also been published under the permissive MIT licence.

The latest RgGen release, and the underlying source code under the MIT licence, is available on the project GitHub repository now.

RISC-V High-Performance Computing SIG Highlights Goals for 2021

The RISC-V Special Interest Group on High Performance Computing (SIG-HPC), which aims to get the free and open source instruction set architecture into future supercomputers, has announced its goals for 2021 — including work to map the existing HPC software ecosystem onto RISC-V.

“The RISC-V Special Interest Group on High Performance Computing (SIG-HPC) was formed to address the requirements of the HPC community and align the RISC-V ISA,” explains chair John Davis. “The SIG is a global committee that works on enabling HPC with the RISC-V ISA and its goal is to enable RISC-V in a broader set of new software and hardware opportunities in the high performance computing space, supercomputers to the edge, and the software ecosystem required to run legacy and emerging (AI/ML/DL) HPC workloads.

“For 2021, SIG-HPC’s goals are to start new initiatives, such as mapping the HPC software ecosystem to RISC-V. This involves automation to discover which open source software, from libraries to benchmarks and applications, work out-of-the-box on the RISC-V ISA. SIG-HPC is starting with the most common libraries like FFT, BLAS, and using GCC and LLVM to compile the codes. The same automation is being applied to benchmarks like HPL and HPCG as well as applications like GROMACS, Quantum ESPRESSO and CP2K. The list is growing! Based on this work, efforts can be targeted to increase library to application coverage by the RISC-V software ecosystem.”

The SIG currently boasts 10 active members from research, academia, and industry, and 141 members on its mailing list — both figures it will be looking to grow as an increasing number of users investigate the potential for RISC-V and other free and open-source architectures in high-performance computing.

“Overall, SIG-HPC’s vision is that of a future where the entire HPC system can be based on open source components,” John says. “Today’s technology trends require specialization to meet the power and performance workload targets. This enables hardware-software co-design, which is a natural fit for open systems, enabling more research and development. The next major milestone for SIG-HPC is to map the HPC ecosystem and develop an associated roadmap. This is where you can get involved!”

More information is available on the RISC-V blog.

FreeRTOS gets Symmetric Multiprocessing Support for RISC-V and Other Platforms

The FreeRTOS real-time operating system has received a major upgrade with the release of symmetric multiprocessing (SMP) support for multi-core systems — building on work carried out by Espressif for RISC-V devices, among others.

“We are really pleased to work with XMOS and other partners to consolidate and upstream the various symmetric multiprocessing versions of FreeRTOS into the officially supported kernel version,” says Richard Barry, FreeRTOS founder. “This enables us, as well as our expansive user community, to provide the same rapid and knowledgeable level of support across an even wider range of innovative processors and use cases.”

The initial release builds on earlier work carried out by Espressif for multi-core RISC-V system-on-chip parts and by XMOS for its xcore multi-core Internet of Things (IoT) platform, consolidating a range of SMP efforts into a single upstream location — offering a dedicated branch of the kernel repository for continued development and collaboration.

“With processes shrinking and approaching the limits of physics, in the last decade we have all got used to multicore chips of increasing complexity and performance extending Moore’s Law in our desktops and laptops,” claims Lucio Di Jasio.

“In embedded control, where cost, size and robustness demands often take precedence over performance, it seems the time for multicore has finally come with the introduction of a number of innovative multicore microcontrollers for IoT, communication, digital signal processing, and Artificial Intelligence. The FreeRTOS community has recognised this rising tide with many contributions aiming at extending the FreeRTOS kernel to support symmetric multiprocessing (SMP) applications.”

The FreeRTOS SMP kernel is available on the project’s GitHub repository now, under the permissive MIT licence. XMOS, meanwhile, has published a white paper on using SMP FreeRTOS on its xcore platform.

Matthew Venn’s Zero to ASIC Shuttle Brings Students’ Designs to Life

Matthew Venn has shown off the student designs from his latest Zero to ASIC course, which teaches how to design students’ own application-specific integrated circuits, which are to be produced as physical chips under the Efabless MPW-TWO shuttle programme.

Projects Matthew has highlighted include a Hogge Phase EMFI/BBI detector dubbed the HP Core, a Fibonacci core, a Pong core, an accelerator core for the ChaCha20 stream cipher, another for the QARMA block cipher, a framebuffer-free video core, Wishbone HyperRAM, and a system-on-chip dubbed Newmot — among others.

Matthew also has a couple of his own designs rounding out the collection: a frequency counter and an RGB mixer. All the designs submitted are fully open-source, as required by the Efabless MPW shuttle programme — under which open-source projects can have their designs built as physical ASICs with production costs covered by Google.

Those interested in seeing the progress of production can follow Matthew’s Twitter account, while anyone looking to sign up for a future Zero to ASIC course can visit the website to be notified when ticket sales open.