El Correo Libre Issue 41

Published in

LibreCores

13 min readAug 10, 2021

FOSSi Foundation Welcomes Jonathan Balkind to the Board of Directors

The Free and Open Source Silicon Foundation is happy to announce today that Jonathan Balkind is joining the board of directors.

Jonathan has been a trusted member of the FOSSi community for many years, where he has shown great skill in solving challenging technical problems, as well as teaching hardware design, and communicating the benefits of doing so openly.

Jonathan is most well-known for his work on OpenPiton, an open source research processor which can be scaled up to multiple million cores.

Within the FOSSi Foundation, Jonathan is managing this year’s Google Summer of Code program, ensuring that many more students are introduced to Free and Open Source Silicon.

Jonathan is currently an Assistant Professor in the Department of Computer Science at the University of California, Santa Barbara.

As Philipp Wagner, Director of the FOSSi Foundation, puts it: “Jon’s a great guy. We’re honoured to have him on the board.”

The board of directors now consists of Julius Baxter, Jonathan Balkind, Philipp Wagner, Stefan Wallentowitz, and Andrew Back. Simon Cook is acting as secretary to the FOSSi Foundation.

CORRECTION:
Last month’s newsletter missed off one of the members of the Google Summer of Code Class of 2021 in an unfortunate transcription error:

Multi-Level TLB Support for Ariane Core (Nazerke Turtayeva)
Mentored by Nils Wistoff and Jonathan Balkind

Your writer apologises for the mistake.

Wavious Releases Free and Open LPDDR4x/5 PHY and Software

Fabless semiconductor company Wavious, which builds its designs around an ecosystem of mix-and-match chiplets, has launch an LPDDR4x/5 PHY with supporting software and made it available under a permissive free and open source licence.

“We are strong believers in open-source hardware and software,” the company announced, “and Wavious is dedicated to making significant contributions to the open source community. Open-source HW [hardware] and chiplets are both necessary to remove barriers to entry and to drive innovation in system design. The WDDR PHY IP has been taped-out in the WLP120 chiplet as part of the Wavious Chiplet Platform ecosystem.”

The release, which is built around the RISC-V instruction set architecture, includes support for LPDDR4x memory at 4,266Gb/s and LPDDR5 memory at 6,400Gb/s. Other features include dual-rank support, a DFI 5.0-compliant memory controller interface, per-bit deskew, and embedded phase-linked loop (PLL), calibration logic, and a training buffer.

Both the hardware PHY and the software, the latter based on FreeRTOS, have been published under the permissive Apache 2.0 licence; full verification testing, however, relies on the proprietary Cadence Simulation Verification IP (VIP) toolchain. Two tests have been published for those without access to Cadence Simulation VIP: a basic boot test which runs the microcontroller at 422MHz and a DDR loopback test running at 2,112MHz.

More information is available from Wavious’ announcement.

Bunnie’s Precursor Gains a Curve25519 Hardware Accelerator

Andrew ‘bunnie’ Huang and colleagues continue to add features to the Precursor, an FPGA-based RISC-V-powered development platform in the shape of a smartphone-like handheld, detailing work on the development of a hardware accelerator for Curve25519 cryptographic operations.

“ I decided to indulge my urge to tinker, and make a custom hardware accelerator for Curve25519 using Litex/Migen and Rust bindings,” bunnie explains. “The fully accelerated Montgomery multiply operation was integrated into a fork of the curve25519-dalek crate, and wrapped into some benchmarking primitives inside Xous, a small embedded operating system written by Xobs [Sean Cross].

“A software-only implementation of curve25519 would take about 100ms per DH operation on a 100MHz RV32-IMAC CPU, while our hardware-accelerated version completes in about 6.7ms — about a 15x speed-up. More importantly, the CPU is free to do other things while the engine does it’s thing, such as servicing the network stack or updating the UX.

“I think the curve25519 accelerator engine hit its goals — it strapped enough of a rocket on our little turtle of a CPU so that it’ll be able render a chat UX while doing double-ratchets as a background task,” bunnie notes. “However, if I were to be honest, it probably wouldn’t be worth it to port the curve25519 accelerator engine from its current FPGA format to an ASIC form.”

The full write-up is available on bunnie’s blog, while the source code is available on GitHub under the permissive CERN Open Hardware Licence v1.2.

RISC-V OpenCL Implementation Aims to Open the ISA to a “Rich Variety” of Workloads

Researchers at the Georgia Institute of Technology and the Oak Ridge National Laboratory have released a version of the OpenCL programming framework for RISC-V parts — supporting everything from resource-constrained microcontroller implementations to Linux-capable application processors

“To the best of our knowledge, there is currently no publicly available implementation of OpenCL targeting commodity RISC-V processors that is accessible to the open-source community,” the paper’s abstract reads. “Besides opening RISC-V to the existing rich variety of scientific parallel applications, OpenCL also provides access to a unique genre of benchmarks useful in computer architecture research.

“Expanding the RISC-V ecosystem to include parallel applications via OpenCL opens the door to the large segment of scientific computing. Furthermore, it provides hardware designers new workloads for exploring new microarchitecture designs and optimisations.”

The team’s OpenCL implementation builds on the work of the Performance OpenCL (POCL) project, adding RISC-V support for both application-class and embedded cores — despite the latter, as the team notes, often lacking support for atomic instructions and multi-threading.

“Our extension [of POCL] particularly targets today’s large segment of commodity RISC-V cores without SIMD vector extensions and also expands to low-profile embedded processors with minimal capabilities.”

The team’s work was presented at the Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), while the code has been published to GitHub under the permissive MIT Licence.

Float Emulation Library RVfplib Takes the SAMOS XXI Open-Source HW/SW Award

Matteo Perotti and colleagues Guiseppe Tagliavini, Stefan Mach, Luca Bertaccini, and Luca Benini have won a SAMOS XXI Open-Source HW/SW Award at the 21st International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation for RVfplib, a floating-point emulation library designed for compact RISC-V cores targeting the Internet of Things (IoT) and other resource-constrained domains.

“Congratulations to Matteo who won the SAMOS XXI open-source HW/SW award for his paper ‘RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors,’” the PULP Platform project announced via Twitter, “which we recently released.”

“Small, low-cost IoT devices rely on floating-point (FP) software emulation on 32-bit integer cores when the cost of a full-fledged FPU is not affordable,” the team explains in the abstract introducing the library. “Thus, the performance and code size of the FP emulation library are decisive for meeting energy and memory-size constraints.

“We propose RVfplib, the first ISA-optimised open-source library for single and double-precision IEEE 754 FP emulation on RV32IM[C] cores. RVfplib is 59 per cent smaller and 2x faster than the GCC emulation library, on average. On benchmark programs code size reduction is 39 per cent and performance boost 1.5x. RVfplib is 5.3 per cent smaller than the leading closed-source RISC-V commercial library.”

Full details are available in the RVfplib paper (PDF), while the PULP Platform has published the library to GitHub under the reciprocal GNU General Public Licence 3.

Antmicro Upstreams its Zephyr FPGA Controller

Antmicro has confirmed it is releasing its Zephyr FPGA controller to the upstream project, in an effort to make it easier to work with FPGA bitstreams within the real-time operating system.

“The Zephyr FPGA controller which we are in the process of upstreaming into Zephyr is the latest example of Antmicro’s work to improve the developer user experience and open up new system design options,” the company announced on its blog. “Enabling both interactive and programmatic use, the FPGA controller allows you to work with FPGA bitstreams from Zephyr without a headache.

“The FPGA controller is a completely new Zephyr subsystem developed to enable communication between Zephyr and FPGAs. The main purpose of the FPGA controller is to enable users to control the FPGA from Zephyr and enable bitstream loading into the FPGA.”

The project includes the creation of a new application programming interface for checking on FPGA status, powering the chip on and off, and changing its contents; FPGA drivers, initially supporting the EOS S3’s embedded FPGA (eFPGA) and the Xilinx US+ FPGA family; and a new shell command within Zephyr for handling the FPGA plus a tool for the loading of arbitrary data into memory.

While the tool has been submitted for mainlining, Antmicro currently recommends that interested parties use its own Zephyr fork — alongside selected usage examples — to get started. More information is available on the Antmicro blog.

MNT Research Releases Kintex-7 FPGA SoM for Modular Reform Laptop

MNT Research has released work-in-progress design files for a system-on-module (SoM) based on the Xilinx Kintex-7 field-programmable gate array, designed for use with the company’s Reform family of modular open-hardware laptops.

“This is [an] open hardware system-on-module featuring the Xilinx Kintex-7 FPGA and 2GB DDR3 RAM,” explains designer and company founder Lukas F. Hartmann of the project. “It can be used as an alternative to the main processor module in the MNT Reform open hardware laptop or in any other custom device.

“The idea is to test synthesised open cores such as CORE-V CVA6 (RISC-V), LiteX (multi-architecture), LibreSOC (OpenPOWER) in a real laptop. True emulation of vintage computer architectures in a laptop form factor is possible as well.”

The module features a Xilinx Kintex-7 XC7K160T-FFG676 FPGA and 2GB of DDR3 memory, a 100MHz main clock oscillator, two USB 3.0 and one USB 2.0 lanes, a four-lane MIPI-DSI display connection, HDMI 1.4, gigabit Ethernet, two PCI Express lanes, three UARTs, two I2C, one SAI, and a pulse-width modulation (PWM) pin for backlight control, and a JTAG header.

The design files for the board, which is currently in the bring-up phase of its creation, have been published on the MNT website under the CERN Open Hardware Licence Version 2 — Strongly Reciprocal licence.

IIIT-Delhi Signs Deal with Thales for Open Hardware Research and Development

The Indraprastha Institute of Information Technology, Delhi (IIIT-Delhi) has announced the signing of a memorandum of understanding (MoU) with technology giant Thales for the development of open hardware projects.

“I am both happy and excited about the signing of the MoU today and the potential it holds for a very productive collaboration between IIITD and Thales,” says Ranjan Bose, professor at and director of IIIT-Delhi. “This collaboration is unique because of the problem-first approach and will leverage complementary skill sets from both sides. This is a long-term strategic partnership and also a step towards strengthening Indo-French collaboration and cooperation.

“We are delighted to join hands with an esteemed institution such as IIIT-Delhi,” adds Thales’ director for India Ashish Saraf. “This partnership comes at an opportune time when technological advancements are fast shaping the world around us. It will draw on the expertise of Thales and scientific talent of IIIT Delhi to enhance research and development in the area of open hardware and related subjects, and contribute to the rich innovation ecosystem in India.”

The signing comes as India seeks to use open hardware to lessen its reliance on foreign technology, with projects including SHAKTI using the RISC-V ISA to build home-brew processors ranging from resource-constrained embedded parts to high-performance server- and high performance compute-centric designs.

More details of the partnership are available in the press release (PDF).

CHIPS Alliance Details Progress on SystemVerilog Open Source Infrastructure

Google developer Henner Zeller has offered a look at the current progress in the development of an open source tooling ecosystem for SystemVerilog, as part of the Deep Dive Cafe Talk by CHIPS Alliance series.

“SystemVerilog is used in a large fraction of the industry, not only at Google but in many companies that actually build state-of-the-art hardware,” Henner explains in the talk. “SystemVerilog is important and relevant for the success of open source tooling.

“SystemVerilog is a huge language, it is not something that you do in an afternoon — or two, for that matter. So what we did is we we set out and said ‘okay let’s find a parser, that’s a good starting point for this SystemVerilog support and then go from there.’”

Henner details a range of projects on this front, including Surelog, sv-parser, and Verible, and how breaking them away from general SystemVerilog support will ease the addition of compatibility into open source toolchains. The talk also takes a look at sv-tests, a verification framework developed by Google and Antmicro and currently under CHIPS Alliance stewardship.

“The development and measurement of different applications to parse SystemVerilog,” CHIPS Alliance general manager Rob Mains notes, “and robustly represent in a common data representation will do much to ensure the development of a solid framework for construction of different design automation tools.”

The full presentation is available on YouTube now, with more information on the CHIPS Alliance blog.

DRAC RISC-V Accelerator Project Details Logic and Physical Synthesis Work

The Designing RISC-V-based Accelerators for Next Generation Computers (DRAC) project at the Barcelona Supercomputer Centre (BSC) has detailed its logic and physical synthesis design flow as it works towards the creation of an out-of-order RISC-V processor which will serve as a high-performance accelerator — and the underpinnings for new post-quantum security and virtualisation techniques.

“In the DRAC project we are designing SoCs (Systems-on-Chip) that include processors based on the RISC-V architecture, different accelerators, and a set of analogue blocks such as a PLL (Phase-Locked Loop), a SerDes (Serialiser Deserialiser), an ADC (Analogue to Digital Converter) and SPADs (Single Photon Avalanche Diodes),” the project maintainers explain in a new update. “Of these analogue blocks, the PLL and the SerDes allow to increase the number of instructions executed by the processor; the PLL allows to increase the working frequency while the SerDes enables faster communications with the external memories. Moreover, the ADC allows interaction with analogue sensors and SPADs are a tool to enable quantum cryptography.

“When planning the integration strategy of the different elements of the SoC, it should be considered that we will work with a mixed signal design. However, as the bigger and the most complex circuits are the digital ones, the chosen strategy is the DoT (Digital On Top). This means that we will start to work as if the SoC were purely digital, and halfway we will add the information of the analogue blocks that have been designed separately.”

The DRAC project’s design flaw post walks through logical synthesis — using, it must be noted, the proprietary Cadence Virtuoso — and the creation of a netlist, the physical synthesis, and the floorplan stages of the process — though without detailing precisely where in its roadmap each lies.

The full post is available on the DRAC website.

2021 Linux Plumbers Conference Gets a RISC-V Microconference

This year’s Linux Plumbers Conference, which opens on Monday 20th September 2021, has accepted a RISC-V-focused microconference onto the schedule — and has opened a call for proposals.

“We are pleased to announce that the RISC-V Microconference has been accepted into the 2021 Linux Plumbers Conference,” the event organisers announced. “The RISC-V software ecosystem is gaining momentum at breakneck speed with three new Linux development platforms available this year. The new platforms bring new issues to deal with.”

Topics under discussion at the event will include progress on platform specification including SBI-0.3 and SBI-0.4 and the new server profile, progress on the RISC-V privileged specification, support for the V and B specifications, work on a KVM port and the H extension’s ratification process, and support for non-coherent systems, among others.

The RISC-V Microconference at last year’s Linux Plumbers Conference covered work on upstreaming RV32 support in glibc, improving the RISC-V platform specification, adding EBBR support, and progress on merging RISC-V KVM support.

More details are available on the conference blog and event schedule; those interested in presenting can apply through the call for proposals page.