El Correo Libre Issue 43

Published in

LibreCores

13 min readOct 12, 2021

Guidelines for Sharing FPGA Designs Published

HDL designs are conceptually at a crossroads between software and hardware. On the one hand, HDL is code. On the other hand, the ultimate object of that code is not to ‘run’ anywhere, but to configure FPGAs or to serve as a basis for the design and manufacture of an integrated circuit.

Because of this hybrid nature, HDL designers have traditionally developed best practices coming from both the software and hardware worlds. It was customary to upload one’s HDL code to a public repository, as software projects do, even before the concept of Open Hardware was formalised.

Today there is no shortage of options when it comes to finding a place on the Web to share your designs, but from the perspective of potential users of these HDL blocks, quality varies widely. Reusability is sometimes also hampered by awkward licensing choices, or by confusion on how to embed or not proprietary code (e.g. blocks automatically generated from the development tools provided by FPGA vendors) in your published design.

OSHWA and the FOSSi Foundation have teamed up to provide guidance on best practices for sharing FPGA designs. The document released this month covers some basics for newcomers to the field and then provides advice on what to publish and how in order to ensure maximum reusability.

For the time being, the guidelines are only meant as a helpful resource for designers who want to share their code efficiently. In the future, they may also serve as a basis for a certification program, similar to what OSHWA already has in place for other types of hardware like PCBs.

-Javier Serrano, OSHWA board member and Open Hardware Repository founder

Vidbo Puts a Virtual FPGA Development Board Into Your Browser

FOSSi Foundation director Olof Kindgren has launched a new open-source project aimed at further lowering the barrier to entry for free and open source silicon projects: vidbo, a virtual development board which runs in the browser.

“I just launched my latest open source project, vidbo, as a way to present a graphical interface to HDL simulations,” Olof announced late last month. “Still in its early phase but launching in the hope to get some feedback and gain interest before everything is set in stone.

“Right now it supports switches, LEDs and UART but to spark your imagination I think the same thing can be used to start/pause simulations, load firmware, turn on/off VCD, print out debug info, inject events in CI and other things. Technically, it’s just JSON objects sent over websockets, so in its essence vidbo is just the protocol and doesn’t require a Verilator back-end and a browser frontend.”

“Thanks to Imagination Technology’s University Programme for sponsoring the initial work, which will also be used in the RVFPGA course. Thanks to Timonsku for doing the initial JS/SVG/HTML work for the PoC. [And] thanks to everyone providing pointers on pointer handling lately.”

The project has been published on GitHub under the permissive Apache 2.0 licence.

RISC-V Privileged Specification v1.12 Enters Public Review

The latest version of the RISC-V Privileged Specification, which adds a range of extensions to the RISC-V standard aimed at improving everything from physical memory protection to virtualisation functions, is now in public review through to the end of this month.

“We are delighted to announce that several specifications have been opened to public review. All of these specifications add functionality to the RISC-V Privileged Specification,” says RISC-V International’s Stephano Cetola of the specification update. “Several important extensions are being reviewed including Version 1.0 of the Hypervisor (H) model, Enhance Physical Memory Protection (ePMP), and several virtual memory specifications.”

Where previous public reviews have focused on a relatively broad group of extensions, however, RISC-V International is taking a different approach this time — splitting things up into smaller, more focused sub-projects.

“With 10 privileged specifications in total, we have broken this public review up into pieces for two reasons,” Stephano explains. “First, we’d like to ensure that each specification receives a focused and thorough review. Second, if any of these specifications require rework before ratification, we do not want that to hold up any of the others.”

The public review period runs until the 31st of October 2021, with discussion taking place on the RISC-V ISA development mailing list.

MNT Research Shows Off Its “First RISC-V Laptop,” Built Around a Kintex-7

MNT Research founder and brains behind the Reform open-hardware laptop Lukas F. Hartmann has shown off what he believes “may be the word’s first RISC-V laptop guts” — after developing a replacement system-on-module for the Reform which replaces the system-on-chip with a Xilinx Kintex-7 FPGA.

“[It’s] hard to describe this feeling,” Lukas writes of the project’s successful first-boot. “Enjoy Digital made a bitfile for [the] MNT RKX7 and I loaded it into the FPGA and it just works. [This] may be the world’s first RISC-V laptop guts.”

Originally built around proprietary Arm cores, the Reform laptop aims to be as open as possible. Hardware design files for everything from the motherboard and system-on-module to the chassis and optional trackball have been released, but the upcoming RKX7 SOM board extends that openness to the silicon itself.

The boot proves the functionality of the new SOM, though the motherboard-and-SOM combo haven’t yet been installed into a Reform chassis to create a finished laptop — and neither has Lukas hinted at when the RKX7 boards may be available to buy.

The commit for RKX7 support in the LiteX project has been published on GitHub under the permissive BSD two-clause licence, while design files for the RKX7 SOM itself are available on the MNT Reform GitLib repository under the CERN Open Hardware Licence Version 2 — Strongly Reciprocal licence.

FPGA Craft Clones a Popular Voxel-Based Game onto the iCEBreaker

Nick Matthijssen has released a Minecraft clone with a difference: FPGA craft runs entirely on the low-cost open-hardware iCEBreaker FPGA development board.

“Last week I spent some time thinking about copyright implications of open sourcing the FPGA Minecraft clone,” Matthijssen wrote, just ahead of actually releasing the project publicly. “To avoid any issues, the open source version will be a ‘light version’ of the project. It won’t include Minecraft specific biomes/structures, so it’s more of a general FPGA voxel game (that happens to be compatible with Minecraft’s textures).

“This won’t really affect the hardware design and firmware/game logic, and there will be a ‘general’ terrain generator. So there should still be enough interesting stuff to check out.”

The FPGA version of the game offers a 256x128 rendering resolution running at a smooth 30 frames per second in 12-bit colour and accepts a Nintendo 64 controller as an input device. The overworld is 512x512x32 blocks, wrapping at the edges, while terrain generation takes place off-device — with new worlds flashed to the board’s memory and changes made in-game being saved back again.

“Use this project at your own risk,” Nick warns anyone interested in trying the open source project themselves. “This project has had no real testing, and unlike typical software, it may have bugs that damage your hardware (board, N64 controller, etc.). Only use it if you’re familiar with FPGA/HW dev and you understand the risks.”

The source is available on Nick’s GitHub repository under the permissive Apache 2.0 licence.

RISC-V GPU Architecture Gains — Unofficial — Support for Nvidia’s CUDA

A team of computer scientists from the Georgia Institute of Technology and Seoul National University has published a paper outlining a pipeline which takes code written for Nvidia’s CUDA general-purpose GPU offload platform and executes it on a RISC-V GPU.

“[The] Nvidia GPU is the most popular choice [in scientific computation] due to its comprehensive documentation and excellent development tools. As a result, there are abundant resources for hand-writing high-performance CUDA codes,” the scientists explain. “However, CUDA is mainly supported by only commercial products and there has been no support for open-source H/W platforms.

“RISC-V is the most popular choice for hardware ISA, thanks to its elegant design and open-source licence. In this project, we aim to utilise these existing CUDA codes with RISC-V devices. More specifically, we design and implement a pipeline that can execute CUDA source code on an RISC-V GPU architecture. We have succeeded in executing CUDA kernels with several important features, like multi-thread and atomic instructions, on an RISC-V GPU architecture. “

The four-stage pipeline takes existing CUDA code and compiles it to NVVM via Nvidia’s own toolkit, translates NVVM into SPIR-V, translates the SPIR-V into OpenCL IR, then finally executes the OpenCL IR on the Vortex GPU — allowing it to run on the RISC-V GPU hardware, instead of the Nvidia GPU for which it was designed.

The team’s paper has been published on arXiv.org under open-access terms, though the researchers warn that “there are still some applications we have not yet supported [which] use either texture or some mathematical functions.”

SweRVolf RISC-V SoC v0.7.4 Brings Down the Barriers to Entry

The latest release of Olof Kindgren’s SweRVolf project, which packs Western Digital’s free and open source SweRV RISC-V cores into a reference system-on-chip design, is out — and brings with it support for smaller and lower-cost FPGA targets.

“The newly supported [Digilent] Basys 3 board is popular within universities, which is a place where we will soon see SweRVolf in its RVfpga incarnation,” Olof explains in an interview with The Register.

The support for lower-cost development boards comes courtesy of the addition of SweRV EL2 core support, on top of the existing SweRV EH1 core. Compared to the EH1, the EL2 core takes up far fewer resources on the FPGA — allowing those looking to experiment with free and open source SoC design to do so on lower-cost hardware.

Other improvements in the new release include support for automatic clock frequency detection when running the Zephyr real-time operating system as a means of boosting binary compatibility between SweRVolf implementations and the release of a new demo showcasing said feature alongside support for simulation in Xilinx XSim 2020.1 and later.

More details on the changes are available on Olof’s blog, while the source code is available on the CHIPS Alliance GitHub repository under the permissive Apache 2.0 licence.

Fstdumper Offers Fast Signal Trace Dumping as a VDI Module

Developer Leo Moser has been in touch to showcase a new tool, fstdumper, which offers easy dumping of waveforms from simulation in the Fast Signal Trace (FST) format — ready for loading into GTKWave and compatible software.

“The idea of this project is to provide an alternative to proprietary waveform formats used in many industry leading simulators,” Leo explains. “Ultimately, most if not all commercial simulators should be supported to dump to FST files.

“On the technical side, the FST dumper from Icarus Verilog has been adapted so that it can be loaded externally as a VPI module. Support for other simulators is currently worked on, hence some iverilog specific features had to be removed. The project is licensed under the GPL-3.0 License.”

At the time of writing the tool supported Icarus Verilog and Cadence Xcelium. “ Community support in testing fstdumper on other simulators is greatly appreciated,” Leo explains. “With your help, we can close the gaps in the compatibility matrix.”

The source code for the project is available in the Semify EDA GitHub repository, following the company’s sponsorship, under the reciprocal GNU General Public Licence 3.

New CoreScore World Record Packs 6,000 SERV Cores into One FPGA

Sylvain Lefebvre is the holder of a brand-new world record for the highest number of SERV RISC-V cores packed into a single FPGA, having managed to squeeze an impressive 6,000 into Xilinx’s Virtex UltraScale+ VCU128.

“We are nearing the max,” Sylvain opines of his efforts, “with 98.5% LUTs [Lookup Tables] (and 100% BRAM [Block RAM]) of the VCU128 FPGA utilised. It’s been great fun working with Olof Kindgren on this, and it was a perfect intro to our Xilinx VCU128 Monster.”

The score of 6,000 cores, as measured using the CoreScore benchmark, soundly beats the previous best of 5,087 cores on a Xilinx Virtex UltraScale+ VCU118 — which, in turn, pushes a 3,040-core score on the Synopsys HAPS-DX7 into third place.

“What do you do when you have the award-winning SERV, the world’s smallest RISC-V CPU,” project creator Olof Kindgren adds. “Well, among other things we of course want to see how many SERV cores you can fit into various devices. This is what CoreScore is for. And on top of that list of currently 30 boards we can now find Sylvain Lefebvre and his Xilinx VCU128 board that fits 6000 SERV cores.”

The current high-score table is available on the CoreScore website, while anyone wanting to have a crack at beating the record can find the source code on GitHub under the permissive Apache 2.0 licence.

Open Hardware Diversity Alliance Aims to Boost Representation in Chip Design

RISC-V International, the CHIPS Alliance, the OpenPOWER Foundation, and Western Digital have announced the foundation of the Open Hardware Diversity Alliance, an effort to boost representation in chip design by offering support programmes, mentoring, learning opportunities, and more to currently under-represented communities.

“Communities benefit from a diverse set of ideas from the broad community. RISC-V is working to build, share, and support these inclusive opportunities by bringing new talent and ways of thinking to the open hardware community,” says Kim McMahon, Director of Visibility and Community Engagement at RISC-V, of the Alliance. “The Open Hardware Diversity Alliance will set the course for inclusivity in the open hardware community by building programs and diversity that inspires creativity and drives innovation.”

“The Open Hardware Diversity Alliance is a huge step forward for the open hardware industry,” adds Marjan Radi, Alliance co-chair and Western Digital technologist. “I, personally, want to make a big impact on not only today’s under-represented individuals, but the many generations to come. Join us and help make this Alliance a valuable and inclusive experience for everyone.”

“When barriers come down, the door to innovation stands wide open,” adds RISC-V International chief executive Calista Redmond. “Together we’re cultivating confidence, connections, and opportunities to strengthen and grow the field as we engage women and minorities in the most innovative and open computing era of our time.”

The Alliance will offer, its founders confirm, a range of programmes supporting the personal and career goals of women and under-represented individuals — and is actively seeking both those who would benefit from its assistance and those who have assistance to offer others.

More details and an application form can be found on the Open Hardware Diversity Alliance website.

Free and Open Source Silicon Contributors Named as Open Source Peer Bonus Winners

A number of free and open source silicon projects can be found among the latest winners of the Google Open Source Peer Bonus, a programme designed for Googlers to nominate external open source contributors for awards in recognition of their efforts.

“I’ve nominated a number of open source contributors for the Peer Bonus programme,” says Google’s Jason Miller. “Since most people volunteer out of passion for a project and expect nothing in return, getting an email from Google thanking them for their contribution carries a lot of meaning.”

Among the 112 winners in the latest round are contributors to number of projects relating to free and open source silicon, including but not limited to Bruno Levy’s Learn FPGA, SymbiFlow, the CHIPS Alliance System Verilog Test Suite, and Verilog to Routing (VTR).

“‘I’ve been active in the open-source community for many years. I’ve often been amazed by some contributors who go out of their way to help me and others; fix bugs, implement features, provide support and do code reviews,” adds Google’s Ram Rachum of the importance of the programme.

“Since I started working at Google, I’ve had the privilege of nominating a few of these contributors for the Open Source Peer Bonus. I’m happy to see their effort get support and recognition from the corporate world. I hope that other big tech companies follow Google’s lead in this regard.”

The full list of winners is available on the Google Open-Source Blog now.