El Correo Libre Issue 45

Published in

LibreCores

10 min readDec 14, 2021

Test Bench Environment cocotb Gets Bug-Fix 1.6.1 Release

October’s release of cocotb 1.6.0, the at-the-time latest version of the popular coroutine-based cosimulation test bench environment for VHDL and Verilog RTL, brought with it a wealth of improvements and new features — and one annoying regression bug, which has now been resolved in version 1.6.1.

Released earlier this month, cocotb 1.6.1 has all the same features as 1.6.0 — including the new C-to-Python PYGPI_ENTRY_POINT, the LogicArray modelling data type, new and improved scheduling functions, and support for ModelSim, Questa, and Xcelium VHDL libraries — but resolves a single regression bug found in TestFactory.

When using TestFactory’s _create_test method in cocotb 1.6.0, the test names are generated without a unique index name suffix — giving all tests the same name. The fix in 1.6.1 corrects this.

Anyone currently running cocotb 1.6.0 or earlier is advised to upgrade to the latest release, which can always be found on the project’s GitHub repository along with the source code under the permissive Revised BSD licence.

Carlos Eduardo Launches Weekly “OpenHWSpace” Twitter Chat

Cloud architect and RISC-V Ambassador Carlos Eduardo has launched a weekly virtual “unconference” series on Twitter Spaces, designed for anyone interested in free and open source silicon, digital design, field-programmable gate arrays, and other topics of interest.

“It’s a non-structured ‘unconference’ where everyone is invited to speak about digital design, hardware, FPGAs, Cores, EDA, and more,” Carlos explains of the weekly event. “I’ve scheduled for a time that is suited from the US west coast to central Europe. So sorry to all Asia and Oceania friends… but the sun doesn’t favour us all!”

The events take place every Thursday at 1500 UTC via the Twitter Spaces platform, a voice chat feature which was opened to all users of the microblogging social media platform in October this year.

To sign up for a reminder for the next OpenHWSpace, see Carlos’ Twitter Space.

Enjoy Digital Turns Old Bitcoin Miners into “100% Open” RISC-V Computers

Enjoy Digital is continuing its work on open hardware with the unveiling of the software and gateware required to turn SQRL Acorn FPGA boards originally developed for Bitcoin cryptocurrency mining into fully-functional RISC-V computers — ready to slot into almost any M.2 PCI Express slot.

“Have a free PCIe-M2 slot in your Linux computer? Why not put a 100% open RISC-V-Linux computer in it or create your own FPGA based accelerator — without any JTAG/UART cable,” the organisation wrote under a short video reveal of the project.

“Funny thing: The LiteUART Linux driver from Antmicro is used on both side for UART communication: By the VexRiscv SoC running Linux and by the Host to create the virtual UART over PCIe. This last missing piece has just been added by Ilia [Sergachev].”

The result is a compact computer running entirely on the compact FPGA, which is then able to communicate with the host over the M.2 PCI Express slot. Using direct memory access (DMA), over 13Gbps communication can be achieved in both directions.

To boost the ecosystem, Enjoy Digital has distributed 20 boards to the community; while those are now gone, anyone interested can find out more on the Enjoy Digital Twitter thread and the LiteX-Boards GitHub repository.

Silicon Compiler Aims to Automate the “Translation of Source Code to Silicon”

The Silicon Compiler project has launched with no small aim in mind: the automation of silicon creation from source code, in the same way a software compiler automatically spits out executable files.

“Compiling simple programs into silicon should be like using llvm or gcc: fast, automated, and accessible,” the projects authors, Andreas Olofsson, William Ransohoff, Noah Moroze, and Zachary Yedidia explain.

“SiliconCompiler is an open source compiler framework that automates translation from source code to silicon using a standardized compiler data Schema, a Python object oriented API, and a distributed systems execution model.”

Silicon Compiler, its creators say, looks to create an infrastucture which can scale to thousands of developers and millions of servers — and yet which makes it as simple as possible to create physical silicon from source code, including a development process which is “like programming in Python: creative, productive, and fun” — and which should take newcomers no more than 10 minutes to go “from Verilog to layout.”

More information on the project is available on the Silicon Compiler website, while the source code and latest release — made available under the permissive Apache 2.0 licence — are both available on the project’s GitHub repository.

Bruno Levy Gets a Ray-Tracer Running on the Tiny SERV Bit-Serial Core

Bruno Levy has given FOSSi Foundation director Olof Kindgren’s award-winning ultra-compact SERV bit-serial RISC-V core a challenging workload: ray-tracing.

Designed for simplicity and size rather than raw performance, SERV is best known as the core used for the CoreScore benchmark — a challenge to see just how many functional SERV cores it’s possible to cram into a single FPGA. As Bruno’s demonstration shows, though, it’s still a functional core in its own right.

Based on a tiny ray-tracing engine written by Dmitry Sokolov and ported to C and RISC-V platforms by Bruno, the project sees the core outputting its image in text mode using ANSI colours for a recognisable if blocky balls-over-chessboard result.

“[I’ve] been thinking of a good demo for a pile of SERVs,” Olof notes of the project’s potential. “The M extension is written also so that an arbitrary number of cores can share a mul/div unit so adding M to a multicore system doesn’t need to cost much extra. My theory is that if you only do a mul every n instructions, then n cores can share a mul without slowdown.”

A video of the ray-tracer running is available on Bruno’s Twitter thread, along with a “TinyTutorial” on how to get it up and running on a Radiona ULX3S development board — and how to make it output to an on-board OLED rather than an HDMI display.

The nextpnr Project Hits a Major Milestone: Its First Tagged Release

The nextpnr project, which aims to offer fully-open vendor-neutral portable place and route capabilities, has hit a major milestone: its first tagged release, nextpnr 0.1.

Hosted as part of the Yosys open synthesis suite project but designed for portability, nextpnr was launched in 2018 as a successor to Versatile Place-and-Route (VPR) and Arachne-PNR. It is built to be vendor neutral, timing driven, and entirely free and open for all to use — and, in the years since its unveiling, has received updates to support a range of target devices, including an experimental “generic” back-end for user-defined architectures.

Development of nextpnr has been rapid and continuous, leaving little room for declaring a point where the project is “ready” — and its first-ever tagged release is numbered v0.1 for that very reason, showing that there’s still plenty of work to be done.

The tagged nextpnr 0.1 release is available on the project’s GitHub repository now, while the source code — which at the time of writing had already seen 16 additional commits since the tagged release — is in the same place under the permissive ISC licence.

nMigen Project Rebrands to Amaranth HDL to Launch a New Era

The nMigen project, an open-source toolchain for Python-based hardware development, is no more — but fans can breathe easily, as it’s continuing under the new name Amaranth HDL — as a means of distinguishing itself from the Migen project.

The newly-rebranded project includes: Amaranth HDL, the hardware description language itself; the Amaranth standard library; the Amaranth simulator; and the Amaranth build system; alongside board definitions, a system-on-chip toolkit, and a WebAssembly-based Yosys distribution.

The name may be new, but the heart of the software is unchanged: those currently building on nMigen can migrate to Amaranth HDL without difficulty, and without losing any functionality.

The rebranding brings the project a new home in the Amaranth GitHub repository, along with a new IRC channel — #amaranth-lang — on the libera.chat network.

Claire Xenia Wolf Warns Against Asynch Load Flip-Flops — As Yosys Gains the Feature

Yosys has gained support for asynchronous load flip-flops, but Yosys developer Claire Xenia Wolf is warning against its use — describing it as a “problematic feature.”

“We have recently added support for asynchronous load flip-flops to Yosys for a customer project.,” Claire explains. “However, we consider this a problematic feature in a (System-)Verilog synthesis tool, and thus I’d like to take this opportunity to explain why one should avoid using asynchronous load flip-flops in new (System-)Verilog designs.

“The way an asynchronous reset is modelled using Verilog always blocks is not sensitive to the data signals providing the asynchronous load value. Thus, if the data signals are changing while the asynchronous reset is active, the new data is not loaded into the flip-flop when neither clock nor the asynchronous reset is toggling.”

Describing this as the “bad news,” Claire also has some good: a series of design methods which can avoid the need for behavioural Verilog code: instantiating flip-flop primitives directly; using a Verilog UDP simulation model; using procedural assign and deassign; and “the latch+flip-flop trick” — which can be used “to completely avoid asynchronous-load FFs while preserving the semantic of such elements.”

The full article, with code examples, can be found on the Yosys blog.

New Learn FPGA Tutorial Puts FemtoRV into LiteX SoCs

Bruno Levy, while not busy making tiny RISC-V cores run ray-tracing engines, has penned a new tutorial for the Learn FPGA series — this time concentrating on putting the FemtoRV core into the LiteX system-on-chip creation framework.

“It is great to have easy access to well written gateware for all the devices available onboard,” Bruno wrote of the project. “LiteX/nMigen [now Amaranth] is a great tool for ‘playing LEGO’ with all these components.

“LiteX can use all the variants of FemtoRV, from the tiniest, femtorv-quark (RV32I), to the biggest one with an FPU: femtorv-petitbateau (RV32IMFC+irq).”

Bruno is currently working on porting a range of demos to the platform, and has already made a ray-tracing engine — the same engine which drove the SERV ray-tracing project detailed above.

The full tutorial, which focuses on targeting the Radiona ULX3S,. is available on the Learn FPGA GitHub repository; supporting video can be found in Bruno’s Tweets.

RISC-V International Celebrates a Bumper Year — and Ratifies 15 New Specs

RISC-V International has released a retrospective boasting of an impressive 130 per cent growth rate for the year and a wealth of achievements — including its most recent: the ratification of 15 new technical specifications representing 40 extensions to the RISC-V instruction set.

“In 2021, RISC-V International made huge leaps in our technical progress as we ratified 15 specifications that are critical for the future of computing,” says board chair Krste Asanović of the organisation’s efforts.

“The development of these specifications really showcased the incredible benefits of open collaboration across companies and geographies as members worked together to develop novel approaches for the latest computing requirements.”

Those 15 newly-ratified specifications includes the Vector, Scalar Cryptography, and Hypervisor specifications — through which it’s hoped to make RISC-V a stronger choice for artificial intelligence (AI) and machine learning (ML) projects, the Internet of Things (IoT), industry, automotive, data centres, and cloud computing.

“RISC-V is proving the power of open collaboration in driving the silicon industry forward with incredible technical advancements, deep global collaboration, and profound innovations across the full spectrum of computing. In 2021, RISC-V has seen unprecedented membership growth in parallel with the rising adoption of RISC-V across markets and geographies,” adds Calista Redmond, RISC-V chief executive.

“I am both proud and grateful for the strategic investment and collaboration of RISC-V members in their technical contributions as we together build RISC-V as the ISA for the open era of computing.”

The full retrospective is available on the RISC-V blog; a list of the most recently-ratified specifications and the extensions they add, meanwhile, can be found on the RISC-V International wiki.