El Correo Libre Issue 47

Published in

LibreCores

14 min readFeb 8, 2022

Cocotb Refresh Finally Explains how to Best Place a Coconut Tree on a Desk

Cocotb, the Python-based coroutine cosimulation test bench hardware verification framework, has unveiled a fully-overhauled website — together with its first-ever official logo.

The new website, available now at www.cocotb.org, provides an entry point for users and not-yet-users of cocotb alike, featuring content like a three-point quick-start guide, a list of key benefits of cocotb, and a section offering a look at the makers behind the project.

Much of this content was to be expected. What may come as a surprise to industry observers, however, is an answer to the long-standing question: where should a coconut tree be best placed on an office desk. As the graphics on cocotb.org show, the answer is simple: coconut trees are to be placed left of the monitor.

It remains a mystery as to why it took the officials at cocotb so long to come to this conclusion.

-Philipp Wagner, Director, FOSSi Foundation

Intel Launches $1bn Fund for Foundry Innovation, Funds RISC-V Development

Chip maker Intel has announced a $1bn fund aimed at what it describes as “early-stage startups and established companies building disruptive technologies for the [chip] foundry ecosystem” — and has, at the same time, joined RISC-V International at the board level.

“Intel is an innovation powerhouse, but we know that not all good ideas originate from within our four walls,” says Randhir Thakur, president of Intel Foundry Services, of the fund.

“Innovation thrives in open and collaborative environments. This $1 billion fund in partnership with Intel Capital — a recognised leader in venture capital investing — will marshal the full resources of Intel to drive innovation in the foundry ecosystem.”

While Intel is best known for its proprietary x86 architecture, the company has also announced that it is increasing its efforts to help build an open RISC-V ecosystem — including joining RISC-V International as a Premier member with a seat on the board and investing funds in RISC-V pioneers including Andes Technology, Esperanto Technologies, SiFive, and Ventana Microsystems.

As part of the investment, Intel Foundry Services will offer a range of validated RISC-V cores, including chiplet-based building blocks, and will sponsor an open-source software development platform.

“A rich open source software and hardware ecosystem is critical for accelerating the growth and adoption of RISC-V and fully unlocking value for chip designers,” claims Intel’s Bob Brennan. “Intel is delighted to support the growth of the free and open RISC-V instruction set architecture.”

“Intel has been a leader in microprocessor innovation for decades and today’s announcements signal the recognition that massive investment in open source has the power to change the course of history,” adds Calista Redmond, chief executive at RISC-V International.

“Open collaboration in RISC-V has already ignited a profound shift in the semiconductor industry, and this partnership will accelerate innovation in open computing. RISC-V welcomes Intel and looks forward to our collective expansion and the commercial adoption of RISC-V across compute workloads and industries, growing RISC-V everywhere.”

More information on Intel’s plans is available on the company press portal.

DuckCore Offers a Fault-Tolerant Twist on the RISC-V ISA

Scientists at the Chinese Academy of Sciences have released a paper detailing a fault-tolerant processor core architecture built atop the RISC-V instruction set architecture: DuckCore.

“DuckCore [is] a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V,” the team explains in the paper’s abstract.

“This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core.”

To prove the DuckCore concept, the team applied the architecture to three existing RISC-V processor cores released under open-source licences: the result, the paper claims, is a design which consumes fewer resources than rival equivalents while increasing portability — and which passes all error injection tests.

The full paper is available under open-access terms on MDPI following its publication in the journal Electronics.

Google Research Releases CircuitTraining for Automated Chip Floorplanning

Google’s research arm has released the source code for its machine learning-based automated chip floorplanning system, detailed in a paper released last year, under a permissive licence.

“Our hope is that Circuit Training will foster further collaborations between academia and industry, and enable advances in deep reinforcement learning for Electronic Design Automation, as well as general combinatorial and decision making optimization problems,” the researchers responsible for the tool write.

“Capable of optimizing chip blocks with hundreds of macros, Circuit Training automatically generates floor plans in hours, whereas baseline methods often require human experts in the loop and can take months.”

The techniques used in CircuitTraining were first detailed in a 2021 paper published in the journal Nature, following their development for in-house use. Now, the code is available to all under the permissive Apache 2.0 licence.

The source code, and a quick-start guide for testing it out with the Ariane RISC-V core, is available on the Google Research GitHub repository now.

The European Commission Proposes a “Chips Act” to Boost Home-Grown Silicon

European Commission president Ursula von der Leyen has raised the possibility of a “European Chips Act,” which would seek to foster development of local silicon design and manufacturing talent and lower the European Union’s reliance on technology from non-member nations.

“The European need for chips will double in the next decade. This is why we need to radically raise Europe’s game on the development, production and use of this key technology,” von der Leyen claimed during an address at the World Economic Forum late January.

“Europe’s global semiconductors market share is only 10% and today most of our supplies come from a handful of producers outside Europe. This is a dependency and uncertainty we simply cannot afford. By 2030, 20% of the world’s microchips production should be in Europe. This means quadrupling today’s European production. We have no time to lose.

“This is why I can announce that we will propose our European Chips Act in early February. It will help us to make progress across five areas.”

Those five areas: an increase in research and innovation; a focus on design and manufacturing; adaptions to state aid rules “under a set of strict conditions” designed to offer public support to “first of a kind” production facilities; improvements designed to anticipate and respond to shortages in the sector; and support for “smaller, innovative companies” in accessing skills, partners, and equity finance.

Full details of the European Chips Act had not been publicly released at the time of writing, but more information can be found in von der Leyen’s speech.

Article image by Etienne Ansotte, © European Union.

Fraunhofer IMS’ Alexander Stanitzki Offers an Intro to TinyML on RISC-V

Engineer Alexander Stanitzki has penned an introduction to Fraunhofer IMS’ work on artificial intelligence at the edge on RISC-V cores — offering an introduction to the permissively-licensed AIRISC core and non-commercial AlfES framework.

“The integration of AI algorithms on end devices (‘Edge AI’, ‘AI of Things’, TinyML,..) is conquering the domain of resource constrained microcontrollers and cost-efficient ASIC designs,” Alexander explains. “AI can improve the performance of basic sensors, helps to achieve light-weight object recognition and tracking in optical detectors and can be useful for HMI functions such as handwriting recognition.

“RISC-V makes it possible to quickly develop new hardware architectures to support these applications even in low-profile and low-cost systems — mainly due to its flexibility and free availability.”

In his blog post, Alexander walks through a real-world example which uses two technologies developed at Fraunhofer IMS: the AIRISC core, a RISC-V implementation designed with embedded AI in mind, released under the permissive Solderpad licence; and AlfES, the company’s embedded AI software framework, released under a reciprocal GNU General Public Licence for non-commercial use.

The full blog post, which walks through the use of dynamic reconfiguration using an embedded FPGA (eFPGA) within an ASIC design, is available on the RISC-V blog now.

Jan Gray Teases An Update to the Composable Custom Function Unit Spec

Jan Gray, of Gray Research, has revealed work in progress on updating the RISC-V FPGA Special Interest Group (SIG) Composable Custom Function Unit Specification, with a public review expected in the coming months.

“A small group of us RISC-V FPGA soft processor experts have been working on HW and HW-SW interface specifications to make it possible for anyone to define new limited scope interoperable custom instruction set extensions, called custom interfaces, and their HW implementations, called custom function units (CFUs), and to compose multiple of them, together with CFU-aware CPUs, into SoCs, and with their accelerated software libraries, into working systems, safely and correctly,” Jan explains.

“I am presently rewriting our spec, the Composable Custom Function Unit Specification. Once the other principals have reviewed and approved my edits, I think we will be ready for public review. Several months.”

“When Zeeshan Rafique added the M extension support to SERV last summer I was hoping to use some standard IF to hook it up because I knew there had been some work on such an IF in the RISC-V FPGA group but I couldn’t find anything,” FOSSi Foundation director and SERV creator Olof Kindgren notes.

“It was just last week that I realized thanks to Karol Gugala that this is now the CFU spec and it’s exactly what I was hoping for. Oh well, time to make SERV CFU-compatible then!”

Public documentation for the original CFU specifications are available on the project’s documentation page, but Jan warns that “many details have changed” since publication.

CFU Playground Offers a Full-Stack Open-Source TinyML Framework for FPGAs

While work is underway to update the CFU specification, meanwhile, a team of computer scientists has been working on making use of its core concepts — releasing CFU Playground, designed as a full-stack framework for edge-AI acceleration on FPGAs.

“Our toolchain tightly integrates open-source software, RTL generators, and FPGA tools for synthesis, place, and route,” the team writes in the paper’s abstract. “This full-stack development framework gives engineers access to explore bespoke architectures that are customized and co-optimised for embedded ML.

“The rapid, deploy-profile-optimisation feedback loop lets ML hardware and software developers achieve significant returns out of a relatively small investment in customisation. Using CFU Playground’s design loop, we show substantial speed-ups (55x-75x) and design space exploration between the CPU and accelerator.

“Future work involves studying the optimisation space for power and energy efficiency. Given CFU Playground’s ability to quickly iterate through the deploy, profile, and optimisation feedback loop, there is an opportunity to integrate CFU Playground into a closed-loop learning-based system that uses machine learning methods to optimise the system automatically.”

The team’s full paper is available on the arXiv.org preprint server; a presentation on the topic, made as part of the tinyML Talks series, can be found on YouTube. The source code has been published to Google’s GitHub repository under the permissive Apache 2.0 licence.

Dustin Offers a 16 Core Cluster with 2-to-32-bit Fully-Flexible Precision

A team working at the University of Bologna and ETH Zurich has unveiled Dustin, a 16-core cluster based on the Parallel Ultra-Low Power (PULP) platform offering two-bit to 32-bit fully-flexible bit precision and a vector lockstep execution mode — offering impressive power savings on suitable workloads.

“Dustin [is] a fully programmable compute cluster integrating 16 RISC-V cores capable of 2- to 32-bit arithmetic and all possible mixed-precision permutations,” the researchers write in the paper’s abstract. “In addition to a conventional Multiple-Instruction Multiple-Data (MIMD) processing paradigm, Dustin introduces a Vector Lockstep Execution Mode (VLEM) to minimise power consumption in highly data-parallel kernels.

“In VLEM, a single leader core fetches instructions and broadcasts them to the 15 follower cores. Clock gating Instruction Fetch (IF) stages and private caches of the follower cores leads to 38% power reduction with minimal performance overhead (< 3%). The cluster, implemented in 65 nm CMOS technology, achieves a peak performance of 58 GOPS and a peak efficiency of 1.15 TOPS/W.”

A copy of the paper is available on the arXiv.org preprint server; Dustin’s code had not, at the time of writing, yet been published to the PULP Platform GitHub repository.

PULP Platform Celebrates a Successful Tape-Out for its Ara Vector Engine

The Parallel Ultra-Low Power (PULP) Platform has received the first chips back from its tape-out of Ara, an implementation of the RISC-V vector extensions for its Ariane core: Yun.

“Yun, the first tape-out of Ara, our RISC-V vector extension engine to Ariane is back from manufacturing,” the organisation announced to Twitter. “We are about to storm the tester room. The Chinese character Yun in this case stands for the Sun 🌞 (not a cloud).”

The Yun chip, which is graced with a picture of an ara macaw on its top layer, is built on a 65nm process at TSMC and packaged as QFN56. The design includes a minimal Ara configuration with four lanes supporting double-precision floating point and 16kB of memory, a further 16kB cache for the Ariane CVA6 core, and 64kB static RAM (SRAM) for the system.

More details on the chip are available in its ISS Chip Gallery entry; information on Ara itself can be found in the original paper, published in the journal IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

MPW1 Submissions Show Signs of Life in a Handy Post-Mortem Carrier

Open-source silicon chips created at SkyWater as part of the MPW1 shuttle, which suffered from serious clock issues owing to issues with the development toolchain, have begun showing signs of life — thanks in no small part to an open-source carrier board for testing.

“[Sylvain ‘tnt’ Munaut” got one of the PyFive MPW-1 chips to say hello today,” Michael Welling announced via Twitter, having worked with tnt to put together a carrier board for chips produced as part of the Google-funded Efabless MPW1 Shuttle fabrication run at SkyWater.

“Due to some issue in the toolchain, it was pretty much expected that those would be completely DOA but turns out, they’re not … totally,” tnt explains. “A combination of a bad clock distribution and a misconfigured timing analysis caused some serious hold violations that were completely missed.”

“The board allows easy access to the pins and provides three adjustable voltage rails,” adds Matthew Venn, whose Zero to ASIC Course submitted a range of chip designs to MPW1 and subsequent shuttles. “An iCEBreaker FPGA board allows us to control the voltage supplies and also provide the firmware by simulating a flash chip.”

Using the board, both tnt and Matthew have been able to bring up parts of their chip designs which were thought to be inaccessible. “I’m pretty confident with some more work I’ll be able to get all 7 segments working,” Matthew explains, “but even if that doesn’t happen it still feels amazing to have my own chips in hand, running my own designs. It’s also great to see that the multiplexing of the projects worked, that the OpenLane tools worked well enough to create a working design.”

The carrier board design has been published to GitHub and OSH Park under the permissive MIT licence; details on its design and use are available in tnt’s video, while Matthew has a write-up on the Zero to ASIC Course website.

RISC-V International Opens New Public Reviews

RISC-V International has announced the release of three new extensions for public review, two review periods for which are still live at the time of publication: the Zmmul extension, and Efficient Trace for RISC-V (E-Trace).

“The Zmmul extension enables low-cost implementations that require multiplication operations but not division,” the draft specification explains. “For many microcontroller applications, division operations are too infrequent to justify the cost of divider hardware.

“By contrast, multiplication operations are more frequent, making the cost of multiplier hardware more justifiable. Simple FPGA soft cores particularly benefit from eliminating division but retaining multiplication, since many FPGAs provide hard- wired multipliers but require dividers be implemented in soft logic.”

Written as part of the Unprivileged Specification, Zmmul is under public review until the 25th of February. The extension is found in §9.3 of the draft specification available on GitHub [PDF], with comments requested via pull request or to the ISA-Dev mailing list.

The non-ISA E-Trace specification, meanwhile, aims to specify the ingress port, compressed branch trace algorithm, and the packet format required for high-efficiency processor branch tracing on RISC-V cores.

“This works by tracking execution from a known start address and sending messages about the address deltas taken by the program,” the draft explains. “These deltas are typically introduced by jump, call, return and branch type instructions, although interrupts and exceptions are also types of deltas.”

The review version of the document is available on GitHub now, with the review period running through to the 11th of March. As before, comments are requested via pull request or to the ISA-Dev mailing list.

RISC-V also launched a public review for the Supervisor Binary Interface Specification in early January, but the review period had closed by the time of publication. The reviewed version of the specification is available on GitHub [PDF].