El Correo Libre Issue 5

In Praise of Documentation

Welcome to the July issue of El Correo Libre! I’d like to start with a thank you to everyone working on free and open-source silicon projects around the world. It’s because of your hard work and dedication that there’s so much to talk about in our monthly newsletters, and frankly it wouldn’t make a scrap of sense for the FOSSi Foundation itself to exist if not for your efforts.
 With all these projects, though, it can be hard to keep track of what’s new, what’s hot, the hows, whys, and wherefores, and even what they’re actually all about. This is why I’m pleased to find so many of this month’s articles focusing on documentation, from step-by-step written tutorials to instructional videos, from project overviews to post-mortem analyses. Whatever the format, they all have one thing in common: they help get out each project’s core message, offering a gentler and more appealing introduction than the unforgiving stone wall of a code repository.
 In the spirit of shared education, I encourage you all to do the following two things this month:

  • Read about others’ projects. You’re sure to learn new things, and perhaps you will even find something to help you over the hump of your own project.
  • Write about your work. There are plenty of people out there — myself included! — who would love to know more about what you’re doing and how they might get involved.

As for me, I’m hard at work on the latter: I have finally started a series of tutorials for FuseSoC, my package manager and build tools collection for FPGA and ASIC development. Just getting things down on digital paper has proven invaluable for finding areas where its usability can be improved, and will hopefully make the project more approachable for others.
 There is, of course, another way to learn more about FOSSi projects from around the world: join us at OrConf 2018 in September to listen to and talk with other developers in the field. What could beat that?
 -Olof Kindgren, Director, Free and Open Source Silicon (FOSSi) Foundation

Will Green Publishes FPGA Graphics Tutorials, Source Code

Engineer Will Green has published a series of tutorials, with support MIT-licensed source code, designed to ease people into developing graphical projects on field-programmable gate arrays (FPGAS).
 “This tutorial series introduces video graphics programming using FPGAs, starting with creating a VGA driver and moving onto more advanced features including bitmaps, sprites and effects,” Will writes on his website, Time to Explore. “FPGAs excel at high-speed I/O and custom logic: you’ll be surprised how much you can achieve with a few lines of Verilog.
 “This series is designed around the Digilent Arty and Basys 3 boards. If you’re using the Arty you also need the VGA Pmod — the Basys3 has VGA output built in.”
 The tutorial posts can be found on Will’s blog at timetoexplore.net, while the source code is available on his GitHub repository. Will himself can be reached on Twitter as @WillFlux.

Verilator Verilog Simulation Tutorials Released by Graham Markall

For those looking to work in simulation, Graham Markall has published three tutorials of increasing complexity detailing the use of the free Verilator simulator.
 Based on Graham’s talk from the Open Source Hardware Camp (OSHCamp) 2018, the tutorials start with the building of a “verilated” model of a simple counter, interaction via testbench, function and task addition, and trace dumping and visualisation for debugging purposes.
 From there, the complexity increases, building up to the implementation of the RI5CY 32-bit RISC-V core, for which a Verilator model and testbench has been created and contributed by embedded specialist Embecosm.
 Graham’s tutorials are available now on his GitHub repository.

FuseSoC Gets Ongoing Tutorial Series

FuseSoC, the popular package manager and build tool collection from the FOSSi Foundation’s Olof Kindgren, now has the first four in a planned series of introductory tutorials.
 “Some time ago I needed to build an emulated GPS device for a project,” Olof writes in the introduction to the first tutorial in the series. “I reckoned it was easiest to do so with an old FPGA board and since this is turned out to be a pretty straight-forward SoC I also realized it would serve well as a tutorial. So here it is, the first tutorial on getting started with building systems using FuseSoC.
 Olof’s tutorial series begins with a guide to getting started, moves on to the creation of a core, then tool options, and finally dependencies, with more entries planned for the future.
 The tutorials are available now on the FuseSoC GitHub repository. The same repository is also host to the latest release of FuseSoC itself, version 1.8.2.

Greg Davill’s Boson Camera Project Continues

Greg Davill is continuing his efforts to build a RISC-V-based driver board for the FLIR Boson thermal camera core, an ambitious first FPGA project discussed in last month’s El Correo Libre — and has received an upgraded camera to test.
 In his latest blog post, Greg details the firmware and the “back of the envelope engineering” that inspired him to create the board in the first place. “The Boson is designed to stream images out automatically, the camera has a control interface, but you cannot simply ask it to ‘snap’ a photo, and read it out byte by byte,” he explains.
 “The biggest benefit of using a softcore processor in my design in my opinion was the ability to leverage existing open source software projects. FatFs is one of those projects, I’ve used it on countless projects in the past,” Greg adds. “The example projects include a ‘barebones’ implementation of the low level control using bit-banged IO. In order to get this to work I just had to extend the GPIO registers from write only to R/W and map them to the SD card pinout in Verilog. With those small changes I was able to write a file to the SD card!”
 Having received an upgraded Boson 640 camera core, with higher resolution, Greg has confirmed he is now working on an upgraded version of his already-functional driver board which can support both cores at full speed.
 Greg’s full update can be read over on his blog.

Kestrel Computer Project Development Videos Hit PeerTube

Sam A. Falvo II has begun publishing a video series detailing the construciton of the Kestrel 3, a project to build a full-stack, open-source, open-hardware home computer based on the RISC-V architecture.
 “In this inaugural episode, I go over a quick history of what I hope to achieve with future episodes, and as well, what I would like to see in the finished results,” Sam writes in the description of the first episode of the Over The Shoulder II video series. “I think it contains some information which might be a good backgrounder, by answering two basic questions: why bother with these videos at all, and also, what does the finished homebrew computer look like in my head?”
 Sam’s follow-up episodes go into more detail regarding the project, including a look at the creation of a DMA controller and the use of test-driven development (TDD) to define Verilog for the interface requirements.
 The video series is live now on PeerTube, while more information on the project itself can be found on its GitHub homepage.

Adam Taylor Details Sobel Edge Detection via High-Level Synthesis

“High Level Synthesis (HLS) allows us to work at higher levels of abstraction when we develop our FPGA application, hopefully saving time and reducing the non recurring cost if it is a commercial project,” writes Adam of his guide to developing a Sobel edge-detection system on an FPGA. “In this project we are going to look at how we can build a Sobel edge detection IP core using HLS and then include it within the Xilinx FPGA of our choice.
 “If we were to implement this within a FPGA using a traditional VHDL / Verilog RTL approach the development time would not be trivial. As we would need to create line buffers for the convolution and then implement the magnitude calculation,” Adam explains.
 “We would also need to create a test bench to so we could ensure our code was working as intended before we progressed to implementation. Luckily when we use HLS we can really skip over a lot of the heavy lifting and let Vivado HLS implement the lower level Verilog/VHDL RTL implementation.”
 Adam’s guide has been published on Hackster.io.

Researchers Release BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay

Yaman Umuroglu, Lahiru Rasnayake, and Magnus Sjalander have published a paper on BISMO, a vectorised bit-serial matrix multiplication overlay for reconfigurable computing, and have released the source code under the BSD 3-Clause Licence.
 “Matrix-matrix multiplication is a key computational kernel for numerous applications in science and engineering, with ample parallelism and data locality that lends itself well to high-performance implementations,” the team write in the paper’s abstract. “We present BISMO, a vectorised bit-serial matrix multiplication overlay for reconfigurable computing.
 “BISMO utilizes the excellent binary-operation performance of FPGAs to offer a matrix multiplication performance that scales with required precision and parallelism. We characterise the resource usage and performance of BISMO across a range of parameters to build a hardware cost model, and demonstrate a peak performance of 6.5 TOPS on the Xilinx PYNQ-Z1 board.”
 The paper is available to download now from arXiv, while the source code can be found on the project’s GitHub repository.

University of Bremen Releases Open-Source RISC-V Virtual Prototype

Researcher Daniel Große of the Computer Architecture Group at the University of Bremen has announced the release of a RISC-V virtual prototype under a permissive licence, along with a functional port of FreeRTOS.
 “The RISC-V based Virtual Prototype (VP) integrates a RISC-V RV32IM core, a PLIC-based interrupt controller, and an essential set of peripherals together with SW debug capabilities,” Daniel’s colleague Vladimir Herdt writes of the project. “The VP is designed as extensible and configurable platform with a generic bus system and implemented in standard-compliant SystemC and TLM-2.0.”
 The release includes full instructions on building both the toolchain and the virtual prototype itself, along with the FreeRTOS port. Links to the GitHub repositories for both the RISC-V virtual prototype and the FreeRTOS port are available from the group’s official website.

Stafford Horne Details OpenRISC GCC Re-Implementation Progress

Developer Stafford Horne has published a detailed post on his progress with re-implementing the GNU Compiler Collection (GCC) for OpenRISC, a project launched in February this year following issues with the copyright of the existing port.
 In the latest of a string of deep-dives, Stafford details GCC’s stack frame definition. “The stack frame layout is very important to get right when implementing an architecture’s calling conventions,” he explains. “If not we may have a compiler that works fine with code it compiles but cannot interoperate with libraries produced by another compiler.
 “For me I figured this would be most difficult as I am horrible with off by one bugs. However, after learning the whole picture I was able to get it working.”
 Stafford’s full write-up is available on his blog shorne in japan, while additional posts are linked from the bottom of the announcement.

Helmut Neemann’s Digital Circuit Simulator Gets Verilog Export Feature

The latest release of Digital, Helmut Neemann’s easy-to-use digital circuit simulator designed with education in mind, now includes the ability to export circuits to Verilog code.
 “Special thanks to Ivan de Jesus Deras Tabora,” Helmut writes of Digital v0.19’s standout new feature, “who has implemented the Verilog code generator and all the necessary Verilog templates!”
 Additional changes in the v0.19 release include the translation of all examples to English, basic support for custom shapes, a “test all” function, and a bug fix for the software’s VHDL output function.
 The latest release is available to download from the project’s GitHub repository now.

Juan Gonzalez Demonstrates IceFactory Automatic Icestudio Block Generation

IceFactory, a JavaScript library for automatically generating blocks for the FPGAwars Icestudio FPGA development environment, has been demonstrated for the first time by creator Juan Gonzalez.
 In a pair of videos published to social networking site Twitter Juan shows IceFactory being used to generate a combinational table with two inputs and four outputs, first at the terminal and then directly from a web browser. In both cases, the block can then be opened directly in Icestudio.
 More information on the project can be found on Juan’s GitHub repository.

OpenPiton Project Announces Seventh Research Processor Release

The OpenPiton project has announced Release 7, which brings a wealth of improvements designed to make the research processor easier for users to implement.
 Based on the UltraSPARC T1 RTL code released by Sun Microsystems in 2006 as the OpenSPARC, OpenPiton aims to develop an open processor core capable of scaling from individual cores for low-power projects up to 500 million cores for supercomputing and highly-parallel initiatives.
 OpenPiton Release 7 includes, among other changes and improvements, a reduction in boot time, the ability to configure the chipset using extensible markup language (XML), and modifications which make it easier to port the processor to as-yet unsupported FPGA development boards.
 The latest release is available now from the official website.

Radiona ULX3S FPGA Board Launched on Kitspace

An open-source FPGA development board design dubbed the ULX3S has been released by Radiona, the Zagreb Makerspace, via the Kitspace platform.
 Measuring 94mm x 51mm, the standalone education-focused board, whose name stands for University digital Logic Learning eXtensible board release 3 with SDRAM, was originally developed as part of a project to create a system-on-chip (SOC) dubbed f32c. The board is based around a Lattice Semiconductor ECP5 FPGA.
 “ULX3S has rich range of chips and connectivity required for many other open source projects,” its creators write. “SDRAM, USB, PS/2, SDCARD, HDMI, FLASH, RTC, I2C, OLED, AUDIO, ADC, onboard FM/ASK antenna 88–433.92 MHz and 56 GPIO pins which are all routed as differential pairs and have pinout that is PMOD compatible. ULX3S is sufficiently equipped to emulate Amiga retro computer and run its games, but can do much more.”
 The board design is available now via Kitspace.

TinyFPGA BX Production Complete, Shipping Begun

Earlier this month Luke Valenty confirmed that production of the TinyFPGA BX development board was complete, and that shipping to Crowd Supply backers had begun.
 “The production TinyFPGA BX boards arrived on July 3rd and are in the process of being tested. This is earlier than planned and will help to pull in the shipping schedule,” Luke wrote to backers. “I am thrilled to have the TinyFPGA BX boards on hand and healthy! I am hard at work to get them tested, packaged, and shipped to backers world-wide.”
 Luke has also released a demonstration of the Atom integrated development environment with the APIO plugin for Verilog on the TinyFPGA BX, publishing a video of the board transitioning from a bootloader heartbeat to running a “blinky” test program via Twitter. “Atom IDE with the APIO plugin ROCKS for developing with Verilog on the TinyFPGA BX,” he wrote. “A fully open-source IDE for developing your project, synthesis with Icestorm, and programming all with the click of a button.”
 More information on the TinyFPGA BX is available on the project’s Crowd Supply campaign page.

OnChip Announces Itsy-Chipsy Call for Participation, New MCU

Open silicon specialist OnChip has promised to issue a call for participation in its Itsy-Chipsy programme, which provides access to ASIC manufacturing on a 180nm process node for under $100, and has already been flooded with projects.
 The company pre-announced the call for participation via Twitter, asking followers what digital chip they would create given a 350µm² area in a 180nm process node. One interesting suggestion to have come out of the replies is the creation of a truly free and open source FPGA fabric, which OnChip describes as “a nice project and doable.”
 OnChip has also teased a new open microcontroller design, via a separate Twitter message, which will include a RISC-V core and analogue functions alongside in-house non-volatile RAM (NVRAM), USB 2.0, and AES cryptographic acceleration, all of which the company pledges to release as open source hardware “soon.”

RISC-V Foundation Announces Security Standing Committee, Issues Call for Summit Papers

The RISC-V Foundation has announced the formation of a Security Standing Committee, which will work with the industry on ensuring the security of the architecture.
 “Security is one of the fundamental issues in our connected world. The RISC-V community is committed to pushing the industry forward through innovative approaches and new thinking to address existing and emerging threats,” says Dr. Helena Handschuh, chair of the RISC-V Foundation Security Standing Committee and Fellow at Rambus.
 “Through open standard collaboration, the Security Standing Committee is fostering the growth of the RISC-V ISA to ensure it meets and exceeds the dynamic security demands of this new era of innovation.”
 More information on the committee is available on the official website. At the same time, the Foundation has issued a call for papers for the RISC-V Summit this December, with more information available on its announcement post.

Western Digital Explains its Attraction to the RISC-V Instruction Set Architecture

The latest issue of Embedded Computing Design has, among other articles sure to be of interest, a piece by Western Digital’s Dr. Zvonimir Bandic on open compute via RISC-V cores and memory fabrics, coming on the back of the company’s plans to ship more than a billion RISC-V cores in the next few years.
 “Big data and fast data pose future data movement challenges,” Dr. Bandic writes, “paving the way for the RISC-V instruction set architecture (ISA) and its open, modular approach, ideally suited to serve as the foundation for data-centric compute architectures.
 “It provides the ability to: scale compute resources for edge compute devices; add new instructions, such as vector instructions for key machine learning workloads; locate small compute cores very close to storage and memory media; enable new compute paradigms and modular chip designs; enable new data-centric architectures where all of the processing elements can coherently access shared persistent memory, optimising data movement.”
 Dr. Bandic’s full piece, along with the rest of the issue, can be read via the Embedded Computing website.

DARPA Kicks Off $100 Million Research Projects for New Chip Design Paradigms

The US Defence Advanced Research Projects Agency (DARPA) has confirmed $100 million in funding for the IDEA and POSH programmes, the brainchildren of parallel computing expert Andreas Olofsson.
 Confirmed by Andreas at the Design Automation Conference (DAC) attended by EE Times’ Rick Merritt, the funding — which comes from the $1.5 billion five-year Electronics Resurgence Initiative (ERI) — will go into the Intelligent Design of Electronic Assets (IDEA) and Posh Open Source Hardware (POSH) programmes in order to solve perceived problems with silicon design and manufacturing.
 “We have to change the culture of hardware design. Today, we don’t have open sharing,” Olofsson told attendees at the event, “I’ve designed a few boards and found it excruciating. [Board designs quickly] explode into hundreds of details you have to worry about in resistors, capacitors, board size … and there are no optimisation tools, so, often, you have a sub-optimal solution. Given the number of boards designed every year, the upside here is enormous.”
 The POSH programme aims to create a library of open source cores and other intellectual property for silicon development, while IDEA targets manufacturing tooling with a push-button flow backed by machine intelligence for turning designs into ASICs.
 More information on IDEA and POSH can be found in a presentation from late last year published to the DARPA website (PDF warning).

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