El Correo Libre Issue 6
Preparing for ORConf 2018
This time of year finds the FOSSi Foundation preparing for ORConf, our annual open source digital design gathering. We felt it might be appropriate to explore the history of ORConf in the newsletter this month, and why we’re proud to run this event.
ORConf, now in its seventh year, was inspired by an informal meeting of OpenRISC project developers in 2011 in a pub in Stockholm, Sweden. It was decided that an annual meeting should be arranged, and ORConf became a reality over a weekend in 2012. That first event was free to attend, and had almost as informal an atmosphere as the pub meet-up the year before. As ORConf has grown over the years, we’ve tried to retain that atmosphere, which we feel helps inclusivity and interaction amongst attendees.
ORConf is no longer exclusive to the OpenRISC project. It is an event which welcomes any and all developers of open source digital design projects. Each year we’re surprised by the number and quality of the works people present. It’s not easy to keep across the projects which emerge from year to year and so to be able to devote a few days to getting up to speed is invaluable, and so too is the ability to have a coffee or a beer with like-minded folks who you may only share email and git pull requests with the rest of the year. It has been fantastic to see the community grow and to see an increasing number of familiar faces each year.
We’ve been lucky to have held this event during a period which has seen incredible advances in the quality and quantity of open source digital design works, and where commodity FPGA platforms and — should you have the means — silicon tapeouts have both become more affordable. That you now have your choice of a dozen or more SoC projects capable of running operating systems like Linux, on commodity hardware, accessible within minutes and usable within hours, is not something you could say eight years ago. Nor could you easily run simulations of such systems, verify and debug them with the impressive range of open source tools now available. Today we even have completely open-source tool chains for some FPGA technologies, which speaks volumes about those contributing to this area and their capabilities. Barriers to entry are lowering at a rapid rate, and that’s been great for the number of people we’ve seen get involved over the past eight years.
This year’s ORConf promises to continue the event’s tradition of quality. I’m very excited to finally have Wilson Snyder along to talk about Verilator, which was open-sourced in 1998; we have a number of presentations on the SymbiFlow tools which are aiming to completely open-source FPGA development; updates from the PULP RISC-V team, as well as updates on the RISC-V efforts in general; a few cocotb Python verification talks; and a number of previous presenters returning to give us an update on their efforts, including an OpenRISC project update two years in the making!
If you can make it this year and want to present your work or get involved by attending, please do. We’re being hosted by the very generous Gdansk University of Technology (Gdansk Politechnika) over the weekend of September 21–23. We look forward to seeing you all!
-Julius Baxter, Director, Free and Open Source Silicon (FOSSi) Foundation
First Shakti C-Class Test Chip Boots Linux
The Shakti processor family, from the Indian Institute of Technology (IIT) Madras, has received its first silicon success story following the booting of a Linux kernel on a 64-bit RISC-V-based open silicon test chip.
Announced during a presentation at the annual RISC-V Workshop and confirmed via Twitter, the project has booted into Linux on a test chip built on Intel’s 22nm FinFET process node featuring a 4x4mm die installed in flip-chip packaging. The chip runs at 320MHz with a 0.7V core voltage, and is part of the Shakti project’s C-class family of mainstream system-on-chip parts.
Discussing the relatively modest clock speed, the project maintainers explained that the current deisgn is “a low-power prototype, [as] we were interested in optimising power and area” with a more performant part due in the future. The project also has additional designs in the works including E-class embedded, M-class mobile multi-core, and H-class high-performance computing (HPC) variants.
The Shakti project also has its first spin-out in the form of Indian start-up InCore Semiconductors, which aims to produce commercial RISC-V-based parts by the end of the year with a focus on combining general-purpose processing and deep-learning acceleration. More information is available from the company’s slide deck (PDF warning.)
More information is available in the team’s presentation video and on the project’s website.
Lawrie Griffiths Publishes Free MyStorm BlackIce II Book, TinyFPGA Brainfuck Port
Developer Lawrie Griffiths has been hard at work of late, announcing a freely downloadable book on the myStorm BlackIce II board and a port of esoteric programming language Brainfuck for the TinyFPGA BX development board.
“I have started writing an ebook on using the BlackIce II based on my experience in making lots of hardware and other projects work and on information from the forum,” Lawrie writes on the myStorm forum. Lawrie also warns: “There are still some sections missing and some sketchy sections. All comments on usefulness and accuracy would be appreciated.”
Challenged by Luke Valenty, Lawrie has also published a port of esoteric language Brainfuck to the TinyFPGA BX. “There are existing implementations in Verilog, but they looked too complicated or not very good, so I implemented my own as I am practising for implementing more serious soft processors,” he explains. “This implementation executes an instruction every clock cycle, other than (uart) input and output. I haven’t implemented input yet. A simple assembler to produce a hex file is included.”
Project Trellis Gets ECP5 Proof-of-Concept Flow, Hello World Demonstration
Following the efforts of David Shah to document the architecture of the Lattice ECP5 FPGA, which hit a milestone detailed back in ECL Issue 4, Project Trellis has now reached a new high: a fully-working Hello World implementation on the chip, and a proof-of-concept flow.
Shown off late last month by David via Twitter, the Hello World demo was the first time the Project Trellis documentation had been used to build a program to run on a physical ECP5 Versa development board.
For those eager to try it themselves, David followed the demo with the release of a proof-of-concept FOSS flow. “Only supports LUTs, FFs and IOs for now,” David wrote at the time, “and expect loads of bugs (issues/PRs much appreciated!) Currently includes blinky-style demos for the @RadionaOrg ULX3S prototype, Lattice ECP5 Versa Board and @TinyFPGA Ex 85k prototype.”
Dave has also proposed an “ultimate ECP5 board,” which would “showcase [the open source ECP5 tools] in their full glory once they are complete — which should be around early 2019. Specifications are available on Twitter, and are open to comment.
Full details of the flow, which uses Yosys, nextpnr, and Trellis, are available on the project’s GitHub repository. David will also be presenting on the project during ORConf 2018 in September.
Shipping Begins for iCE40-Based BeagleWire FPGA BeagleBone Capes
QWERTY Embedded Design’s Michael Welling has confirmed the receipt of the first batch of BeagleWire FPGA development capes for the BeagleBone single-board computer, with shipments to backers having started earlier this month.
Funded via a Crowd Supply campaign, the BeagleWire is a fully open-source development board featuring the Lattice Semiconductor iCE40HX FPGA. All schematics, software, and firmware are available under permissive licences, while the chip itself is programmed using the open source IceStorm toolchain.
The crowdfunding campaign closed in April this year, at an impressive 150 percent above its goal, and the initial production run included excess boards which can be purchased now for immediate shipment for $85 (exc. taxes, international shipping).
More information is available on the campaign page.
Rust Language Receives Official RISC-V Support
Developer David Craven has announced the acceptance of a pull request to add support for the RV32IMAC RISC-V architecture to the Rust programming language, allowing support to be installed via the rustup tool.
Designed to be a functionally safe language for highly-concurrent systems, David’s pull request enables an LLVM backend, ABI and build target for the 32-bit RV32IMAC RISC-V architecture — allowing developers to build Rust programs for RISC-V implementations using the built-in riscv32imac-unknown-none-elf target.
Alex Bradbury, code owner for the RISC-V LLVM port, thanked David and the others who had worked on the project in a message on GitHub. “I’d love to see support for Rust on RISC-V Linux targets too, though it’s worth noting there are other pre-requisites beyond the atomics support that isn’t fully merged (e.g. hardfloat ABI, PIC, TLS),” he added. “We should make better use of the upstream LLVM bugzilla to keep track of unimplemented features that are useful to the Rust community.”
More information is available in the pull request, while those wishing to experiment can install the Rust toolchain with RISC-V support via rustup now.
Luke Valenty’s TinyFPGA BX In Stock and In-The-Wild
Luke Valenty’s TinyFPGA BX, discussed in our interview with him from ECL Issue 3, has come back into stock for new orders following shipment to Crowd Supply campaign backers in mid-July — and they are now available from Tindie and SparkFun as well as Crowd Supply.
With backers having received their TinyFPGA BXes, projects have started to be published. Miya has shown off a portable music generator which generates its own infinte music in real-time, written in Java and converted to Verilog using the open-source HLS compiler Sythesijer. Spencer Owen, meanwhile, has published a video using the TinyFPGA BX to demonstrate general FPGA concepts.
More information on the TinyFPGA family, which is to be extended with the planned launch of the larger TinyFPGA EX in the near future, is available on the official website.
If Luke weren’t busy enough, meanwhile, he has also announced a port of the Daisho USB3 core to the Lattice Semiconductor ECP5–5G, as part of his work on the upcoming TinyFPGA EX. His current progress can be found on GitHub.
PULP Platform Project Announces QuickLogic eFPGA Integration Plan
ETH Zürich has confirmed a partnership with QuickLogic Corporation to add the company’s ArcticPro embedded FPGA (eFPGA) technology to the Parallel Ultra-Low Power (PULP) Platform, with the company’s chief technology officer praising PULP’s “multi-disciplinary approach.”
“The high degree of implementation flexibility and ultra-low power consumption of QuickLogic’s eFPGA technology make it a perfect complement to the extreme power efficiency objectives we have for the PULP Platform,” explains Dr. Luca Benini, director of the PULP Platform and one of its originators. “We are excited to integrate this technology to evaluate hardware/software implementation trade-offs, and we are particularly interested in exploring feature extraction functions for AI at the edge and security applications.”
“The main goal of the PULP programme is to use a multi-disciplinary approach to achieve extremely high-power efficiency for computing applications,” adds Dr. Timothy Saxe, QuickLogic’s chief technology officer. “QuickLogic has a tremendous depth of experience in achieving low power consumption across a broad range of applications, including AI and IoT at the edge and security, and we look forward to contributing what we’ve learned along with our eFPGA technology to this groundbreaking initiative in low power computing.”
The PULP Platform is detailed on the official website, while Davide Rossi will be giving a talk on the project at ORConf 2018 in September. Frank Gürkaynak, who leads the PULP Platform’s ETH Zürich team, has also published an illuminating piece on his work: Utilising Open Source Hardware in Academic Environments.
Dan Gisselquist Writes on Synthesis and Simulation Mismatches
Gisselquist Technology’s Dan Gisselquist, not pictured, has published an article on common reasons why a synthesised core might not match the simulations.
“I asked on Reddit for a list of things that might cause your simulation not to match reality,” Dan explains. “When I asked, I thought I knew most of the reasons. To my surprise, the kind Reddit readers were glad to share with me many more reasons why simulation might not match actual hardware performance.”
Reasons detailed in the piece including timing, metastability, blocking versus non-blocking assignments, a poor simulation model, and, interestingly, an asynchronous reset triggered by spurious radiofrequency signals. “I wouldn’t have believed this one myself if I hadn’t come across it while browsing Xilinx’s forums,” Dan adds.
Dan’s full write-up is available on the ZipCPU blog, while Dan will be among the presenters at ORConf 2018 in September.
Sigrok Project To Receive SUMP2 Support
Developer Rangel Ivanov has announced they are working on adding support for Black Mesa Labs’ SUMP2 open-source logic analyser for FPGAs to the portable cross-platform Sigrok signal analysis software suite.
“Adding @sigrok support for @bml_khubbard’s SUMP2,” Rangel writes on Twitter of the work. “Small progress but it’s a progress right :D Tomorrow will try to work on reading the captured data. I’m planning to implement reading non-RLE data first.”
“Support for Black Mesa Labs’ SUMP2 Logic Analyser is being added to the Sigrok project,” adds BML’s Kevin Hubbard. “I am ecstatic to say the least.”
More information on the two projects are available on the Sump2 GitHub repository and the Sigrock website.
RISC-V Pioneer SiFive Launches E2 Core IP, Announces Design Wins
SiFive, founded by members of the team responsible for the creation of the open RISC-V instruction set architecture, has announced the release of a new E2 Core IP along with design wins that will see RISC-V powering three commercial products: the Annapurna solid-state drive controller and Bravo SSD from Fadu, a programmable SSD platform for developers from Mobiveil, and eSilicon’s next-generation 7nm SerDes IP.
Each company praised the RISC-V ISA and SiFive’s implementation thereof. “We chose to partner with SiFive on this SSD platform solution as their cores offer the lowest area and highest power efficiency of any similar cores in the market,” says Ravi Thummarukudy, Mobiveil CEO; “SiFive’s RISC-V Core IP was 1/3 the power and 1/3 the area of competing solutions,” adds Fadu’s chief executive Jihyo Lee, “and gave FADU the flexibility we needed in optimizing our architecture to achieve these groundbreaking products.” “SiFive’s E2 Core IP allows eSilicon to provide the flexibility and configurability that our customers require while achieving industry-leading power, performance, and area,” concludes eSilicon’s Hugh Durdan.
The SiFive E2 Core IP, meanwhile, is a RISC-V-based microcontroller designed for embedded use, launching in two flavours: E21, with “mainstream performance,” and the E20, with improved power efficiency.
With numerous design wins under its belt, including providing core IP that will be used in storage giant Western Digital’s upcoming RISC-V-based products, SiFive is clearly demonstrating that free and open source silicon can — and will — ship at scale.
Hobbyist Site Hackaday Launches FPGA Boot Camp Tutorial Series
In a move which will hopefully get more hobbyists interested in the field of free and open source silicon, electronics hobbyist site Hackaday has launched a tutorial series aimed at newcomers to field-programmable gate arrays: the Hackaday FPGA Boot Camp, aimed at those familiar with software programming looking to make the leap into hardware.
“These boot camps gather together some of the material you seen spread over many articles here before, plus new material to flesh it out,” explains Hackaday’s Al Williams. “It’s designed for you to work through more like a training class than just some text to read. There’s plenty of screenshots and even animations to help you see what you are supposed to be doing. You’ll be able to work with simulations to see how the circuits we talk about work, make changes, and see the results. We’ll focus on Verilog — at least for now — as it is close to C and easier for people who know C to pick up.”
The tutorials are live now on Hackaday.io.
Serge Bazanski Employs Verilog for Capture The Flag Challenge Victory
Serge Bazanski, contributor to open-source silicon projects including the nextpnr place and route tool, has written of an unusual use-case for Verilog programming: solving the Code Blue Capture The Flag Qualifier challenge.
“The binary would present a WATCH_DOGS-style minigame style challenges to the user, who would solve them by rotating ‘joints’ until they guided a signal from a source to a goal (in later stages, multiple goals at once). After solving five stages, the program would display a flag read from a file and exit,” Serge explains of the challenge. “When you get to the third stage, however, the binary stops showing you visualizations. It’s time to dig deeper.”
“How do we solve a puzzle like this? It might simply be the case that I’m in the proximity of a mind-altering hammer that makes me hallucinate everything to be a nail… but I chose converting the puzzles to Verilog and using formal methods to find solutions.”
Serge’s full write-up is available on the Dragon Sector website.
Researchers Publish LeFlow TensorFlow High-Level Synthesis Tool
Researchers Daniel H. Noronha, Bahar Salehpour, and Steven J.E. Wilton from the Department of Electrical and Computer Engineering of the University of British Columbia have published a paper detailing a tool for converting TensorFlow deep neural network code into synthesisable Verilog: LeFlow.
“in this paper, we present an open-source tool-flow that maps numerical computation models written in TensorFlow to synthesisable hardware,” the team explain in the paper’s abstract. “Unlike other tools, which are often constrained by a small number of inflexible templates, our flow uses Google’s XLA compiler which emits LLVM code directly from a Tensorflow specification. This LLVM code can then be used with a high-level synthesis tool to automatically generate hardware. We show that our flow allows users to generate Deep Neural Networks with very few lines of Python code.”
The tool, which uses the open-source LegUp High-Level Synthesis framework, has been published to GitHub under a permissive licence. The paper, meanwhile, is available for open access on arXiv (PDF warning.)
Researchers Praise RISC-V, Open Silicon Ecosystems for Security Assurance
Researchers and engineers from Galois and Bluespec have published a paper on a formally verified cryptographic extension for the RISC-V architecture, noting that the openness of the ecosystem provides new opportunities to avoid the security issues currently plaguing closed-source silicon.
“In software, security assurance cases typically rely upon well studied cryptographic foundations and development artefacts open to peer review, such as formal protocol specifications, formal algorithm specifications, and proofs of correctness,” the team explains. “In hardware, however, security assurance is nearly always based upon secrecy and limited amounts of testing, with no formal proofs and minimal, if any, peer review.
“The open RISC-V ecosystem presents an opportunity to change the state of system security assurance for the better, by enabling for hardware the open peer review and independent formal verification already available for high assurance software. As a proof of this concept we have built a formally verified cryptographic extension to RISC-V, incorporated it into a small system, and developed an assurance case spanning the system’s hardware, firmware, and software. Here, we primarily describe the cryptographic extension and the assurance techniques we used to verify its correctness, as compared to typical assurance techniques used for validated cryptographic systems.”
The full paper is available on the project’s GitHub repository (PDF warning).
Rick Altherr Details the Xilinx 7-Series Bitsteam
Software engineer Rick Altherr has been writing a series of blog posts detailing his work in unpacking the bitstream of the Xilinx 7-series FPGA, after work on writing manipulation tools for the SymbiFlow project.
“After building a mostly-working implementation in C++, I started to wonder what a generic framework for FPGA development tools would look like,” Rick explains. “Inspired by LLVM and partly as an excuse to learn Rust, I started a new project, Gaffe, to prototype ideas. With Xilinx 7-series fresh in my mind, I chose to reimplement the bitstream parsing as a first step. While most of the bitstream format is documented in UG470 7 Series FPGA Configuration User Guide, [PDF warning], subtle details are omitted that I hope to clarify here.”
Split into, at the time of writing, Part One, Part Two, and Part Three, the post series will prove invaluable to anyone working with Xilinx 7-series parts at the bitstream level. Rick will also be giving a presentation on the analysis, which is known as Project X-Ray, at ORConf 2018 in September.
Matthew Zamora’s Fipsy FPGA Begins Reaching Project Backers
Matthew Zamora’s low-cost beginner-friendly and breadboard-compatible Fipsy FPGA break-out board has begun reaching users who backed the project through its Kickstarter campaign.
Designed to be accessible to beginners, sold at a price point of just $10 (exc. taxes and shipping), and using only free- and open-source design tools, the Fipsy campaign proved popular, raising several times its modest $3,500 funding goal from over 700 backers. Those backers have now started to receive the boards, with people as far afield as Fresno, US and Bradford, UK reporting that the parts have arrived.
“This is the kind of project that empowers others, and that helps us empower ourselves,” Matthew wrote in a campaign update just prior to shipping commencement. “As people share the projects they are working on, we can all learn!”
More information is available on the official website.
Fedora Linux on RISC-V: A Hands-On Field Report
Tommy Thorn has published a brief report on the Fedora RISC-V port in practical use, firing it up in the QEMU emulator and experimenting with variables including minimum permissible RAM.
“I spent a few hours doing actual work completely inside QEMU running Fedora/RISC-V,” Tommy writes in a Twitter post. “It was nearly uneventful. The SW is very far along. Fantastic work by the @fedora team behind it!”
Queried about how much RAM the system needs in order to operate properly, Tommy added: “Single core 256 MiB appears to boot as smoothly as 4 GiB,” before clarifying that 256 MiB proved too little to run the dnf package manager. “192 MiB boots, but slower. At 128 MiB you run into problems where the firewall doesn’t want to start. Unscientifically, it feels like 256 MiB is a minimum. 512 MiB worked better.”
Instructions on downloading and booting the Fedora RISC-V port are available from the official website.
Designing Custom Chips In-House Is The New Normal, Says Paul Teich
Writing for Next Platform, DoubleHorn analyst Paul Teich has declared the age of custom silicon upon us — and with companies including Amazon, Alibaba, Baidu, Facebook, Google, and Microsoft all in the silicon game now, it’s hard to argue with his conclusion.
“Chip design and manufacturing is being disrupted by a new set of technical and economic enablers. Cloud giants designing AI chips is just the tip of a mass-customisation asteroid impacting the computer chip manufacturing supply chain,” Paul claims, pointing to the ready availability of silicon IP in proprietary licensable or open-source form as a key factor.
“RISC-V aims to democratise compute-intensive repeatable structures with open source processor cores,” he adds. “Alibaba, Cadence, Google, GlobalFoundries, Huawei, IBM, Mellanox, Mentor, Qualcomm, and Samsung are listed among its members.
“A web giant with control of its own software operating environments and deep learning modelling language will also have access to chip design talent and tools, the best of open source and licensable IP blocks, and can build prototype chips and then run high volume production silicon anywhere on the planet. The web giant can customize its integer and floating-point processor cores. It can build SoC designs with custom processor cores, custom AI accelerators, custom I/O and memory controllers, etc. And it can optimise its in-house software performance on its in-house chips in ways that general purpose software development tools can’t approach on mass-market chips. The following year, the web giant might design completely different chips.”
Paul’s full piece is available on Next Platform now.