El Correo Libre Issue 7
Google Summer of Code 2018 Retrospective
As in previous years, the FOSSi Foundation has participated in this year’s Google Summer of Code. In this programme Google provides three-month scholarships to students worldwide, allowing them to contribute to open source projects. Even more important than the actual code contributions, the students are encouraged to become active members of open source communities and to learn how those communities work. This way the students become long-term contributors, even after the scholarship is over.
The FOSSi Foundation participates as a so-called umbrella organization: we provide projects related to Free and Open Source Silicon, EDA tools, and the ecosystem to participate in Google Summer of Code with our help. Each of the students gets mentored by maintainers of the projects, and the FOSSi Foundation organises the administrative part and supports both the students and mentors.
This year we had six great projects:
- Sandip Kumar Bhuyan has been involved with our very own project, LibreCores.org. He has improved the discoverability of cores on the portal with a search function and categories, a feature we have all been hoping for. You can find his summary of the project here.
- Kunal Gulati has worked with the team around Prof. Michael Taylor from the University of Washington on the Basejump project. This project aims to simplify the design flow, and Basejump STL is a collection of library modules for it. Kunal worked on the mathematics functions and summarised his project here.
- Ahmed Salman has worked with Steve Hoover of the Transaction-Level Verilog project. He contributed to the base of a component library and summarised his summer of code here.
- Sriyash Caculo has contributed to the MyHDL project by contributing to the digital filters and the integration with the PyFDA project. He has summarised his work here.
- Noe Nieto worked on the DEVSIM project, towards the simulation of solar cells with the Beer-Lambert algorithm. He furthermore contributed an object-oriented API to the project and summarised his work here.
- Ákos Hadnagy has worked on the formal verification of the WARP-V processor, an open source implementation of the RISC-V ISA implemented in TL-Verilog. His work can be followed here.
We thank all students and mentors for their great work. It is great to see so much interest in the FOSSi community, and the Google Summer of Code continues to be a great opportunity for us to support and grow the free and open-source silicon ecosystem. We are looking forward to Google Summer of Code 2019!
-Stefan Wallentowitz, Director, Free and Open Source Silicon (FOSSi) Foundation
Clean-Room OpenRISC GCC Port Rewrite Submitted Upstream
Developer Stafford Horne has announced the submission of a clean-room rewrite of the OpenRISC GNU Compiler Collection (GCC) port, following issues with copyright assignation for sections of the original port’s source code.
“OpenRISC has a mature GCC port started in early 2000s. The issue is it is not upstream due to one early contributor not having signed over his copyright,” Stafford explained in a blog post from February this year.
“To get around this I discussed options with the group and in the end I opted for a clean room rewrite,” Stafford continues in a message to the gcc-patches mailing list late last month. “The new code base has been written by me and more recently Richard Henderson. I trust that both of us have our FSF GCC copyrights in place.”
“I have forwarded your request to the GCC Steering Committee to formally accept the contribution,” David Edelsohn confirms in a follow-up post. “The port still requires a technical review and approval from a GCC Global Reviewer. You mentioned Richard Henderson as co-author. If Richard signs off on the port, approval could be relatively quick.”
The clean-room GCC rewrite can be found on Stafford’s GitHub repository.
DarkRISCV Unveiled as “RISC-V Implemented From Scratch in One Night!”
In what may be one of the most impressive demonstrations of the accessibility of modern free and open source silicon, developer Marcelo Samsoniuk has released what he claims is a functional RISC-V implementation created in just one night.
“Developed in a magic night of 19 Aug, 2018 between 2am and 8am, the DarkRISCV is a very experimental implementation of the opensource RISC-V instruction set,” Marcelo explains of the project. “Nowadays, after weeks of exciting sleepless nights of work (which explains the lots of typos you will [find] ahead), the DarkRISCV reached a very good quality result, in a way that the “hello world” compiled by the standard riscv-elf-gcc is working fine!
“The general concept is based in my other early RISC processors and composed by a simplified two stage pipeline where a instruction is fetch from a instruction memory in the first clock and then the instruction is decoded/executed in the second clock. The pipeline is overlapped without interlocks, in a way the DarkRISCV can reach the performance of one clock per instruction most of time (the exception is after a branch, where one clock is lost in the pipeline flush). As addition, the code is very compact, with around two hundred lines of obfuscated but beautiful Verilog code.”
Based on the RV32I instruction set and working up to 75MHz, DarkRISCV is available now from Marcelo’s GitHub repository under the BSD Licence.
GreenWaves Opens GAP8-Based GAPUINO Board Sales Ahead of ORConf Workshop
RISC-V pioneer GreenWaves, which developers the GAP8 application processor implementation with a view to Internet of Things (IoT) suitability, has officially opened sales for an Arduino-inspired development board based around the chip: the GAPUINO.
Featuring nine RISC-V cores — split into one controller core and an eight-core parallel compute cluster — and based on the Parallel Ultra-Low Processor (PULP) Platform, the GAPUINO is based on the popular Arduino Uno board layout, includes a camera connector, 256Mb of quad-SPI flash storage, 512Mbs flash and 64Mbs DRAM on a HyperBus, USB connectivity for JTAG and UART, and can be configured for 3.3V or 5V logic.
Optional accessory boards are also available: a sensor board, which adds four microphones, a VL53 time-of-flight sensor, infrared sensor, pressure sensor, light sensor, temperature and humidity sensor, and a six-axis accelerometer and gyroscope sensor; and a low-power QVGA-resolution image capture board with black and white sensor.
Pricing for the boards has been set at €100 for the GAPUINO alone or €199 for a bundle featuring the GAPUINO, sensor board, and image sensor add-ons, while the sensor board and image sensor are available separately for €80 and €40 respectively. The GAP8 processor is available as a bare engineering sample chip priced at €400 for ten. (All prices exclusive of VAT.)
More information, and links to purchase the boards, can be found on the official website, while attendees of ORConf 2018 can attend a hands-on workshop centred around the GAPUINO.
Matt Kimball Releases “Toy GPU” Core for Luke Valenty’s TinyFPGA BX
In a demonstration of just what’s possible on the next-generation TinyFPGA BX, the latest model in Luke Valenty’s TinyFPGA family of open hardware FPGA development boards, Matt Kimball has released a fully-functional graphics processing unit (GPU) core capable of rending 3D line primatives.
“I implemented a simple GPU on a TinyFPGA BX, which accepts a list of lines to draw over an SPI bus,” Matt explains in a forum post introducing the project. “The lines are transmitted as screen coordinates with begin and end points. It then renders those lines at 640x480@60Hz and displays them via a VGA connector.
“Since the TinyFPGA BX lacks enough RAM for a full framebuffer, each scanline is rasterized just prior to display and then discarded to make space for the following scanlines. At no time is a full rendered image in memory. I’m driving the GPU with a Raspberry Pi. This is my first FPGA and first Verilog project, so I probably did some silly things there, but I was proud of the result, so I thought I’d share it.”
A demonstration of the core in use, rending Suzanne the Blender Monkey, is available on YouTube, while the source is available under an unspecified licence on Matt’s GitHub repository.
SUMP2 with DeepSump to HyperRAM Ported to BML S7 Mini Development Board
Developer Kevin Hubbard has released a port of the SUMP2 logic analyser with DeepSump to HyperRAM support for the Black Mesa Labs Spartan 7-based S7 Mini FPGA development board.
“This is a full FPGA design. 200 MSPS of 32 channels,” Kevin writes of the port on Twitter. “DeepSump DRAM add-on has a sustainable bandwidth of around 10 MSPS, so usable for bursty time acquisitions at 200 MSPS, or for sampling lower speed signals (say SPI at 15 MHz) but maintaining 200 MSPS asynchronous sample resolution. Size of FIFO determines burst limits.
“Only about 10% of the LUT and Registers are used in a 7S25. Using 75% of BRAMs — but that was deliberate. Can use way fewer BRAMs and still be quite functional. The BRAM is maxed out using 8Kx64 for the RLE/Normal SUMP2 sampling and then also a 4Kx108 FIFO for DeepSump interface to HyperRAM. Scaling back to just 256x64 and 256x108 is quite usable for limited capturing scenarios when RLE works its magic.”
The port is available for download now on the Black Mesa Labs SUMP2 GitHub repository.
Open-Silicon Retro-uC Microcontroller Project Hits Crowd Supply
The Chips4Makers’ Retro-uC, an open silicon project designed to bring vintage compute cores including the Zilog Z80 and MOS 6502 to modern makers and tinkerers, has officially opened its crowdfunding campaign after being unveiled at ORConf 2017 last year.
“I am delighted to announce that the Retro-uC Crowd Supply campaign has now been launched,” Chips4Makers’ Staf Verhaegen says of the project. “It has taken a little longer to straighten out the last hurdles in production and delivery but now the campaign is waiting for you.
“Next to the hardware targets now also open silicon development support is included in some of the targets. This is to help to bootstrap the low-volume open silicon movement. This is the first step on the road to low-volume low-cost open silicon. I much appreciate any support or expertise you can provide in this endeavour.”
The Retro-uC board design borrows its layout from the Arduino Mega family, but features the ability to run processors cores including the Zilog Z80, MOS 6502, and Motorola M68K, known to vintage computing enthusiasts as the power behind the Sinclair ZX Spectrum/Timex 2048, Commodore VIC-20, and Commodore Amiga, among other well-regarded classic computers.
More information is available on the Crowd Supply campaign page, which runs through to late October with pledges ranging from chip-only to full-board layouts.
GreenWaves’ RISC-V-Based GAP8 Design Praised by EC CORDIS Study
A report from the European Commission’s Community Research and Development Information Service (CORDIS) has praised the “novel architecture” of GreenWaves’ RISC-V-based GAP8 processor for its potential to improve both energy and spectrum efficiency in future Internet of Things (IoT) wireless communication projects.
The High Efficiency Access Solution for the Internet of Things (HEASIT) study saw GreenWaves developing commercial technologies designed for low-power wide-area network (LPWAN) use, and was a key part of the development of the RISC-V and PULP Project based GAP8 processor and GreenOFDM frequency division algorithm.
“One of the project partners developed a fully programmable solution in the form of a multicore processor with a unique energy efficiency,” the report explains of GreenWaves’ creation. “The architecture built on two world-class open-source projects (RISC-V and PULP), which is a very novel approach in the semiconductor industry. At system level, they combined an emulation of GreenOFDM with the open-source protocol stack long-range wide-area network to successfully realise point-to-point radio communications.”
“The HEASIT innovation dramatically reduces the cost of deploying and operating rich sensors in the field,” adds project coordinator Loic Lietar, chief executive of GreenWaves. “Consequently, this enables a much larger number of those sensors and ultimately significantly enriches the spectrum of IoT use cases.”
More information on HEASIT is available from the CORDIS website.
Marek Materzok Releases Yosys/DigitalJS Verilog Visualisation Demo App
The University of Wrocław’s Marek Materzok has published a live demonstration web app for a Verilog visualisation system, based on the DigitalJS digital logic simulator.
“This is a demonstration page for the DigitalJS digital logic simulator and the yosys2digitaljs netlist format converter,” Marek writes. “This demo was made possible by the Yosys open-source hardware synthesis framework. It is a web app with a Node backend.”
Running in the user’s browser the software aims to visualise and simulate any System Verilog code pasted or loaded, and comes with examples including SR latch, D latch, full, serial, and accumulating adders, a linear-feedback shift register, ROM, and RAM which can be selected from a drop-down dialogue. Actual synthesis and simulation takes a few seconds for each example, and is fully interactive.
The demonstration app is available live on the official webpage, while its source code can be found on the GitHub repository under an unspecified licence.
Dan Gisselquist Explains How to Build an SPI Flash Controller Core
Dan Gisselquist has published a piece on building an SPI flash controller for an FPGA, as part of the ongoing ZipCPU project to create a formally-verified open silicon processor.
“Perhaps you may remember that I’ve been working to port the ZipCPU to an iCE40 HX8k platform: the ICO board,” Dan writes by way of introduction. “I like to boast that the ZipCPU was designed for low logic applications, and the iCE40 is certainly a low logic chip. While the ZipCPU isn’t the smallest processor out there, there are some forth processors that are much smaller, it does fit nicely with room to spare on the iCE40 8k.
“However, if you want a design that starts immediately upon power up, or if you want more memory than is available in 8kB of block RAM or (in this case) even in 128kB of SRAM, then you need access to the flash memory. I also had another reason for this project as well: I wanted to learn about System Verilog sequences, and whether or not they could be used to formally verify a flash controller. Yes, I had access to the full commercial (Verific enabled) version of yosys to do this. But I wanted to see how useful this full version would be when it came to designing a new/better flash controller.”
Dan’s write-up walks through his history of flash controller development, a look at how SPI bus works, configuration port implementation, a look at the Verilog code, and formal verification, ending with a functional and proven read-write capable flash controller.
The full write-up is available on the ZipCPU Gisselquist Technologies website.
RISC-V Foundation Issues Update on Software Toolchain Status
Jim Wilson, of RISC-V Foundation member SiFive, has issued an update on the status of the RISC-V software toolchain ecosystem — and progress is most definitely being made.
“Over the past few years the RISC-V ecosystem has grown tremendously. The RISC-V Foundation now has more than 100 member organisations and we’ve seen a number of innovative RISC-V solutions hit the market,” Jim writes. “Meanwhile, the community has been hard at work contributing to the development of the RISC-V software toolchain to make it even easier to use the free and open instruction set architecture (ISA).
“As part of this development, companies and individuals from around the world have been working to bring RISC-V ports upstream so the ports can be more easily maintained. Initially, updating RISC-V toolchain ports was done on copies of the official source trees before the updates were ready to be submitted upstream. Now, most of the ports have been submitted to the upstream trees so RISC-V development work is primarily happening in the upstream trees where developers are tracking release branches and backporting bug fix patches onto them.”
Of the projects mentioned in Jim’s post, the statuses are: GCC, binutils, and newlib have been fully upstreamed; QEMU has been upstreamed though with a patch backlog; and GDB, glibc, and the Linux kernel are all partly upstreamed.
Jim’s full post is available on the RISC-V Foundation blog, while RISC-V Foundation member AntMicro will be offering a further update during ORConf 2018.
FOSSi News In Brief
- FuseSoC Receives Picosoc Support, Nextpnr Support for iCE40
- Registration Now Open for VSDOpen Conference 2018
- Chisel Community Conference 2018 Opens Call for Contributions
- Semiconductor Engineering on “Bugs That Kill”
- RISC-V Foundation Launches “Last Week in RISC-V” Newsletter
- Pulse Density Modulation Example Added to iCEBreaker Repository
- InnovateFPGA Unveils Bus Spider RISC-V-Based Multitool
- FμPy FPGA MicroPython Language Adds Arty A7 Support
- JAEB on “Using FPGAs for Audio Processing”
- Build a (Simple) CPU In-Browser with The NAND Game
- Zephyr Project Adds RISC-V Support, New Members
- SiFive Launches SoC with Nvidia’s NVDLA AI Tech On-Board
- CNXSoft on LicheeTang’s Anlogic EG4S20 RISC-V Focused FPGA