El Correo Libre Issue 8
ORConf 2018 A Rousing Success
ORConf has come and gone for another year, and first of all the FOSSi Foundation would like to thank everyone who attended, presented and sponsored. The event saw 30 talks and a dozen lightning talks spread across three days at the beautiful Gdansk University of Technology. Enough can’t be said of the calibre of this year’s presentations, and attests to the ever-increasing quality of open source works we’re seeing developed.
The event began with Zvonimir Bandic from this year’s title sponsor, Western Digital, presenting its internal development of a major open source IP and the motivation for doing so. We heard updates from multiple stalwart open source hardware projects in the RISC-V Foundation, the PULP project, and the OpenRISC project, which finally got its GCC upstreamed thanks to the effort of Stafford Horne.
Saturday began with a tour de force of the open source FPGA tooling efforts, hearing from Tim Ansell on SymbiFlow, David Shah on the Lattice FPGA support developments, and the eminent Clifford Wolf talking about his latest efforts for FPGA place and route with the nextpnr project. After lunch we were very pleased to finally welcome Wilson Snyder to the floor at ORConf to hear about his latest work on Verilator. Then, after a flurry of cocotb talks in the afternoon, the day was capped off with a panel discussion on the challenges and opportunities open source hardware faces.
The heavens opened on Saturday evening in Gdansk, but that didn’t dampen spirits as the conference dinner, this year generously sponsored by Jane Street, was well attended and provided a great environment to have a few drinks and longer-form discussion about some of the topics which had come up so far. Sunday’s topics touched on RISC-V CPUs, SoC debug, more DSLs, and finally some VHDL verification presentations capping off a seriously impressive set of presentations. The slides from all of these will be available on the ORConf site shortly, and the videos of presentations will be made available within a few weeks.
We’re extremely pleased that ORConf continues to be a place for open source hardware developers to catch up with each other, share updates and hear about new projects which are almost always of interest, in a relatively informal environment. What continues to impress, too, is the enthusiasm amongst the community, which helps give the volunteers at the FOSSi Foundation the impression that they’re doing something right. The Foundation will be running more events in the very near future, so keep an eye on the orconf-announce list.
Finally, a big thank you to Marek Wójcikowski and the Gdansk University of Technology for hosting us this year. A big thank you to all of our sponsors as well — ORConf is free to attend due to you guys, so thanks a bunch! And thanks again to everyone who travelled to Gdansk this year to be with us; we’re very much looking forward to seeing you all again at our next event.
-Julius Baxter, Director, Free and Open Source Silicon (FOSSi) Foundation
PULP Platform Announces Heterogeneous Research Platform HERO
The team behind the Parallel Ultra-Low Power (PULP) Platform has officially unveiled the project’s latest design: HERO, an open heterogeneous research platform based on a RISC-V many-core accelerator.
“HERO combines a PULP-based open-source parallel many-core accelerator implemented on FPGA with a hard ARM Cortex-A multicore host processor running full-stack Linux,” the team explains. “HERO is the first heterogeneous system architecture that mixes a powerful ARM multi-core host with a highly parallel and scalable many-core accelerator based on RISC-V cores.
“HERO offers a complete hardware and software platform which advances the state of the art of transparent accelerator programming using the OpenMP v4.5 Accelerator Model. The programmer writes a single application source file for the host and uses OpenMP directives for parallelisation and accelerator offloading. Lower-level details such as differing ISAs as well as shared virtual memory (SVM) between host and accelerator are handled by our heterogeneous toolchain based on GCC 7, runtime libraries, kernel driver and our open-source hardware IPs. As such, HERO greatly simplifies heterogeneous systems programming and forms a complete basis for future system-level research and industrial design comprising both the hardware and software side of heterogeneous systems.”
Created to support the Eurolab-4-HPC2 project, HERO is based on a Xilinx Zync ZX706 evaluation board running an eight-core 32-bit RI5CY-based “Mr. Wolf” PULP cluster with 256KiB of shared L1 scratchpad memory, 4KiB of shared L1 instruction cache, 256KiB of shared L2 scratchpad and instruction memory, and a newly-developed “Remap Address Block (RAB)” input–output memory management unit (IOMMU) featuring 32 variable-size entry L1 and 1,024 page-size entry transaction lookaside buffers (TLBs).
More information is available on the project’s documentation site, while the software development kit and bigPULP IP can be found in their respective GitHub repositories under the Apache Licence 2.0 and SolderPad Hardware Licence 0.51 respectively.
Workshop on Open Source Design Automation (OSDA) Launches Call for Contributors
The organisers of the Workshop on Open Source Design Automation 2019, held in conjunction with the Design, Automation, and Test in Europe Conference (DATE), have opened a call for contributors with a submission deadline of the 17th of December 2018.
“This one-day workshop aims to bring together industrial, academic, and hobbyist actors to explore, disseminate, and network over ongoing efforts for open design automation, with a view to enabling unfettered research and development, improving EDA quality, and lowering the barriers and risks to entry for industry,” the event’s organisers explain. “These aims are particularly poignant due to the recent efforts across the European Union (and beyond) that mandate ‘open access’ for publicly funded research to both published manuscripts as well as any code necessary for reproducing its conclusions.”
Topics of interest are listed as including, but not being limited to, open-source FPGA tools, open-source IP to run on said FPGAs, design methodologies provided as open-source including alternative hardware description languages (HDLs), suggestions for weaknesses and future directions for the open-source FPGA movement, and case-studies on licensing, funding, and commercialising open-source hardware projects.
Submissions are being accepted through to the 17th of December 2018, while the event itself is to take place on Friday the 29th of March 2019 in Florence, Italy. More information is available on the official website, with a link for submission to appear in the near future.
FOSSi Foundation Announces First Bay Area FOSSi Fiesta Event
The Free and Open Source Silicon Foundation (FOSSi Foundation) has announced FOSSi Fiesta, informal community-driven meet-ups with talks and discussion, starting with the Bay Area FOSSi Fiesta on the 14th of October.
“The afternoon of October 14 will see the first Bay Area FOSSi Fiesta event. A semi casual meetup for everyone interested in Open Source Silicon,” the event’s organisers explain. “Join us for some FOSSi fun. There will be a couple of presentations and time to sit down and discuss with fellow FOSSistas. Afterwards we go out and eat together for those who are interested.”
The first event will be hosted by Western Digital in San Jose, the Foundation has confirmed. While the Bay Area FOSSi Fiesta is free to attend, registration is required so that numbers can be managed. Interested parties can register to attend, and optionally to present at, the event or simply find out more on the by official website ahead of the closure of applications at noon PST on the 11th of October.
William D. Jones Ports MicroPython to the TinyFPGA BX
Developer William D. Jones has announced success in a project to port the popular MicroPython programming environment, a Python subset designed for use on microcontrollers and embedded processors, to Luke Valenty’s TinyFPGA BX open hardware development board.
“As of about 30 minutes ago, @TinyFPGA’s BX board now has full support within @mithro’s litex-buildenv tool,” William wrote of the GitHub pull request through which the project began. “Why is this important to me, a random FPGA dev, you ask? Litex-buildenv support paves the way for TinyFPGA to support MicroPython!
“As of about 3 minutes ago, I now have a Micropython prompt from TinyFPGA BX,” William wrote on Twitter just two days later. “Support will be pushed soon, still need to prepare a few things. Also will come up with a more meaningful demo.”
That demo came in the form of a seven-second video showcasing MicroPython working directly on the TinyFPGA BX, praised as “awesome work” by board designer Luke Valenty. The port has not yet been publicly released, but progress can be tracked on William’s GitHub profile.
For those looking for more on the TinyFPGA BX itself, Dan Gisselquist has written a detailed overview on the ZipCPU blog, including an interview with Luke, while Elektor Magazine’s Clemens Valens has published a review which describes it as “a serious board that can be useful in many applications.”
Verilator 4.0 Launched at ORConf
Wilson Snyder officially launched the latest version of the Verilator tool, Verilator 4.0, at the ORConf 2018 event — bringing multithreaded model generation for the first time.
Originally a Digital Equipment Corporation (DEC) Core Logic Group product, Verilator was built to convert Verilog code to C code. Having been used to assist in the development of DEC’s Alpha processor, the company chose to release its source code under a permissive licence in 1998. Wilson Snyder took over as maintainer in 2001, working with the community to rewrite the tool in C++ and in doing so making it one of the fastest conversion utilities of its type — around 100 times faster than its interpreted Verilog simulator competition.
The Verilator 4.0 branch, formally announced by Wilson Snyder during ORConf 2018 following a period of early availability, includes a selection of improvements and enhancements over the older 3.9 branch. Chief among these improvements is the addition of multithreaded model generation functionality, significantly improving performance on modern multi-core processors to up to ten times its single-core predecessor, along with optimisation for large blocks, support for runtime arguments, and a selection of fixes for bugs in earlier versions.
The latest version of the tool, at the time of writing, is Verilator 4.004; more information on this release, along with installation and usage documentation can be found on the Veripool website.
Western Digital Publishes Fedora GNOME RISC-V Build Guide
Storage specialist Western Digital, as part of its initiative to switch over to the open RISC-V instruction set architecture across its storage processing product portfolio, has published a full guide to building, installing, and booting the GNOME Desktop variant of Fedora Linux on the RISC-V-based SiFive HiFive Unleashed development board.
“The intent of this document is to share the hardware setup and source code build instructions to bring up Fedora 29 GNOME desktop on HiFive Unleased board,” writes Western Digital’s Atish Patra. “It is assumed that you know how to set up a RISC-V development environment.”
The instructions require both the HiFive Unleashed board itself, which is based on SiFive’s Freedom U540 64-bit RISC-V system-on-chip (SoC), plus the Microsemi HiFive Unleashed Expansion Board add-on, a Caicos-based AMD Radeon graphics card, a PCI Express USB adapter, and SATA or NVMe storage for the operating system itself. “It is not recommended to use an image from a microSD card,” Atish warns.
Following the instructions, the user should end up with a fully-functional Linux desktop — proving the potential of RISC-V and similar free and open source silicon endeavours as alternatives for mainstream desktop-class processors.
The full tutorial can be found on the Western Digital GitHub repository.
“It’s Time for New Computer Architectures,” Says David Patterson
RISC-V Foundation vice chair David A. Patterson, joint recipient of the 2017 ACM A. M. Turing Award for his work on the RISC-1 processor prototype that would become Sun’s SPARC architecture and the textbook Computer Microarchitecture: A Quantitative Approach, has renewed his call for novel computer architectures while declaring the era of Moore’s Law over.
Speaking at the @Scale 2018 conference, attended and reported by IEEE Spectrum, David declared the industry to be “a factor of 15 behind where we should be in Moore’s Law were still operative,” referring to the observation turned hard target by Intel co-founder Gordon Moore that the number of transistors on a leading-edge processor tends towards a doubling roughly every 18 months. “We are in the post-Moore’s Law era.”
That provides opportunity for innovation, David claimed: “This is a golden age for computer architecture,” he told attendees, echoing the title of a joint lecture delivered with John L. Hennessy at the International Symposium on Computer Architecture (ISCA) 2018 conference. “Revolutionary new hardware architectures and new software languages, tailored to dealing with specific kinds of computing problems, are just waiting to be developed. There are Turing Awards waiting to be picked up if people would just work on these things.”
A summary of David’s presentation at the event can be found on IEEE Spectrum.
Arm Responds to Growing FOSSi Threat with ‘Free’ Cortex IP
Embedded processor giant Arm has announced a new initiative to provide developers with Cortex processor IP specifically for use with FPGAs — but its offerings are very much free-as-in-beer, rather than free-as-in-speech.
Following the company’s disastrous decision to launch a marketing site designed specifically to attack RISC-V, Arm’s response to the growing interest and commercial distribution of FOSSi IP has taken a shift: the company is now releasing Cortex-M1 and Cortex-M3 core IP under no-payment licence terms, in an effort to convince developers to stick within its own ecosystem and on the Arm architecture.
Built on the company’s existing DesignStart programme, the offer sees the Arm Cortex-M1 core — a variant of the Cortex-M0 tailored for FPGA use — made available immediately, while the more powerful Cortex-M3 will be made available some time in November. To use the cores, developers must be using approved Xilinx FPGAs and agree to a licence which precludes their use in reverse engineering, for pruposes outside product development and shipping, and for benchmarking against other cores.
Details of Arm’s programme can be found on the company’s DesignStart FPGA site.
RISC-V Foundation Launches Soft CPU Core Design Contest
The RISC-V Foundation took to the stage at ORConf 2018 to announce the launch of a soft CPU core design contest, in partnership with Google, Antmicro, and Microsemi and targeting the 32-bit RV32I architecture with or without additional standard extensions.
The contest is to be scored across four metrics: smallest implementation on Microsemi SmartFusion 2 or Igloo 2 and on Lattice iCE40 UltraPlus FPGAs; and highest-performance implementation on the same FPGAs. The ‘smallest’ metric is to be scored based on the total resources used, including logic elements, math blocks, and internal RAM, with performance used as a tie-breaker; the ‘highest-performance’ metric is to be scored via the Dhrystone benchmark compiled with -O3 and -fno-inline options.
Entries must be provided in Verilog, pass the RV32I ISA test, and boot the Philosophers and Synchronisation Zephyr applications, and are to be submitted in the form of GitHub repositories with a BSD-style licence. 25 each of boards featuring MIcrosemi’s Igloo 2 and SmartFusion 2 FPGAs are being made available for entrants free of charge, upon application. First prize is $6,000; second prize is $3,000 plus a Splash Kit and iCE40 UltraPlus MDP; and third prize is $1,000 plus a PolarFire Evaluation Kit and iCE40 UltraPlus Breakout Board.
Full details on entering are available from the official website, with entries due by the 26th of November.
Dan Gisselquist Releases Open-Source Pipelined FFT Generator
Dan Gisselquist, of Gisselquist Technology and its ZipCPU project, has released a tool for generating custom Fast Fourier Transform (FFT) cores, along with a detailed guide to its development and use.
“I needed an FFT that could process two incoming samples per clock, or I would have no chance of applying my FFT based GPS processing algorithm in real time,” Dan explains of his inspiration. “Since building this core, I’ve discovered how universally applicable an FFT core is. As a result, I’ve expanded the initial FFT capability that I had built in order to handle some of the more common use cases. Not only does this FFT process a high speed input at two samples per clock, but it can now handle the typical case of one input sample per clock, or even half or a third of that rate. Part of my hope with this change is to be able to easily process audio samples at rates much slower than the FFT pipeline can handle.”
To support his work with FFT cores, Dan’s generator creates an FFT of arbitrary size with a range of configuration options. “These features make this open source pipelined FFT module very different,” Dan explains, “and unique among the other open HDL cores you may find.”
Dan’s blog on the project details the purpose of an FFT, the creation of the generator, its use, and formal verification of the cores it creates. The tool itself, meanwhile, is available on GitHub under the GNU General Public Licence 3 — though Dan has indicated he is considering “relicensing this with a more permissive licence.”
FOSSi News In Brief
- RISC-V 1.0 ‘Trainwreck’ source uploaded to GitHub for ‘archaeological’ purposes.
- Embecosm adds 64-bit RISC-V support to Buildroot.
- Steve Hoover, Akos Hadnagy detail WARP-V RISC-V core generator.
- Domipheus Labs continues RISC-V FPGA CPU tutorial series.
- Hackaday runs a round-up of iCE40-compatible open-source tools.
- Icestudio receiving iCEBreaker FPGA development board support.
- RISC-V added to the Linux Plumbers’ Conference.
- Semiconductor Engineering says “RISC-V is pushing further into the mainstream.”
- Turning an iCEstick board into a “terrible radio transmitter.”
- Kevin Hubbard ports BD_SHELL diagnostic tool to Python.
- Clifford Wolf announces his appointment to the RISC-V Bitmanipulation Task Group.
- Hackaday highlights a round-up of popular low-cost FPGA development boards.
- RISC-V Foundation releases Inaugural RISC-V Summit (Santa Clara, December 2018) agenda.
- A recap of the Third Bay Area RISC-V Meetup.
- Western Digital waxes lyrical about RISC-V in ongoing video series.
- Rambus shows how easy it is to build with RISC-V.
- Huami releases RISC-V-powered wearables into the market.