El Correo Libre Issue 9

ORConf 2018 Videos and Slides Now Available

As detailed in our last El Correo Leibre newsletter, the recently-held ORConf 2018 event was a great success, with many fantastic talks, hallway discussions, and valuable insights into other projects relating to the free and open source silicon ecosystem.

If you were unable to attend, if you need a refresher on how great the talks were, or if you are looking for archival copies for future reference, don’t despair: the videos and slides from the event’s numerous presentations are now available online!

Thanks must be given to the hard work of Simon Cook, who did all the video editing. Thanks to his efforts, you can now watch — almost — all talks on our YouTube channel.

The slide decks from most talks are also available online: you’ll find them next to the talk descriptions on the ORConf page.

With ORConf 2018 behind us, we are already in the process of collecting location proposals for ORConf 2019 — so if you have an interesting location available and would like to host ORConf next year, please do get in touch with us!

-Philipp Wagner, Director, Free and Open Source Silicon (FOSSi) Foundation

Edalize Split from FuseSoC, Released as Python Library

Free and Open Source Silicon Foundation director Olof Kindgren has announced the release of edalize, a Python library designed for interfacing with FPGA tools.

Originally developed as part of the FuseSoC package manager and build tool collection for hardware description language (HDL) projects, edalize is now available as a separate Python library which can be used in other projects that interface with electronic design automation (EDA) tools, such as simulators and synthesis utilities.

“The FuseSoC EDA tool interfacing backends have now been split out to a separate library called edalize and can be installed with ‘pip install edalize’,” wrote Olof in an announcement on Twitter. “So if you have a project that talks to EDA tools, consider using and contribute to edalize.”

Edalize is available now from Olof’s GitHub repository.

LowRISC 0.6 Milestone Release Published

Developer Alex Bradbury has announced the launch of lowRISC 0.6, a milestone release which improves the core clock frequency of the Rocket RISC-V, adds support for debugging via JTAG, and improves the project’s Ethernet functionality.

“This release includes an updated version of the Rocket RISC-V core, a higher core clock frequency, JTAG debugging support, Ethernet improvements, and more,” Alex writes in the announcement. “See the release notes, for full details. We’ve also taken the opportunity to re-organise our documentation, adding an easy to follow quick-start guide.

“Our next development focus is to add support for dropping in the Ariane RISC-V design (from ETH Zurich) as an alternative to Rocket.”

The latest release is available from the project’s GitHub repository, where any issues encountered should also be reported.

01xz.net Targets Verilog Students with HDLBits Practice Exercises

Educator Henry Wong’s 01xz.net — named for the four-state logic used by nets and variables in Verilog — is offering those looking to learn the language free circuit design exercises, ranging from the simple to the more challenging.

“HDLBits is a collection of small circuit design exercises for practising digital hardware design using Verilog Hardware Description Language (HDL),” Henry writes of the project. “Earlier problems follow a tutorial style, while later problems will increasingly challenge your circuit design skills.

“Each problem requires you to design a small circuit in Verilog. HDLBits gives you immediate feedback on the circuit module you submit. Your circuit is checked for correctness by simulating with a set of test vectors and comparing it to our reference solution.”

Organised by topic and approximate level of difficulty, the exercises range from a simple introduction to Verilog and HDLBits itself to combinatorial logic, sequential logic, finding bugs and creating circuits based on waveforms output by simulations, and writing non-synthesisable testbenches. Simulations can be run in-browser using a web interface for Icarus Verilog.

The exercises can be browsed now on hdlbits.01xz.net.

Yosys Open Synthesis Suite 0.8 Released

Developer Clifford Wolf has released version 0.8 of the popular Yosys open-source Verilog hardware synthesis framework, bringing with it a range of bugfixes and improvements including initial support for the Coolrunner-II, eASIC, and ECP5 platforms in the back end.

Released under the same BSD-like, GPL-compatible ISC licence as previous versions, Yosys 0.8 is a recommended update with a wealth of improvements even for those not using the newly-supported back-end platforms: the update includes support for new SystemVerilog features, new commands, an extended API, new formal verification features, an improved Verific front-end, extended iCE40 support, and support for MAX10 and Cyclone-IV family synthesis including an example implementation aimed at the MAX10 development kit.

The full changelog is available on the Yosys GitHub repository, along with a link to download the source code.

DATE 19 Conference Gets Workshop on Open-Source EDA for FPGAs

The Design, Automation, and Test in Europe (DATE) 2019 conference has confirmed a workshop on open-source design automation (OSDA) for FPGAs, run by Eddie Hung, Christian Krieg, and Clifford Wolf, with submissions open through to the 17th of December.

“This one-day workshop aims to bring together industrial, academic, and hobbyist actors to explore, disseminate, and network over ongoing efforts for open design automation, with a view to enabling unfettered research and development, improving EDA quality, and lowering the barriers and risks to entry for industry,” the organisers explain. “These aims are particularly poignant due to the recent efforts across the European Union (and beyond) that mandate ‘open access’ for publicly funded research to both published manuscripts as well as any code necessary for reproducing its conclusions.”

Topics listed as of-interest to the workshop, though not to the exclusion of others, are: open-source FPGA tools, open-source intellectual property (IP) for FPGAs, design methodologies provided as open-source, directions on potential future directions for the open-source FPGA movement, and discussions and case studies centred around licensing, funding, and commercialising projects based on open-source hardware.

Full details of the event, which is to take place on the 29th of March 2019 as part of the DATE 19 conference in Florence, Italy, can be found on the official website.

OnChip Completes E31 RISC-V-based Microcontroller Chip Design

Colombia-based semiconductor company OnChip has announced the completion of its 32-bit RISC-V microcontroller design, which blends a SiFive E31 RISC-V core with numerous analogue components design to appeal to sensor builders and embedded designers.

First announced by OnChip back in May, the open-silicon Open-V design is designed for low power sensor applications, and includes features such as a true random number generator (TRNG), 12- and 10-bit digital to analogue (DAC) and analogue to digital (ADC) converters, and a brownout detector.

Issues were discovered with the design, however, which led to a delay in its launch — issues the company has now resolved, it claims. “After more than a month at the lab bringing up the chip and overcoming a fastidious bug, the [E31 RISC-V] based core and all the peripherals are working as expected,” the company declared via Twitter. “Low-power ADC/DAC, POR, BOD, RCO, LDO, biasing ckts and LFXTAL intended for low-duty-cycle sensor nodes.”

OnChip has not yet announced when it plans to make parts available to the general public.

Nextpnr “router1” Gets a Major Rewrite

“Router1,” part of the nextpnr place and route tool project, has received a major rewrite in a pull request published by Clifford Wolf this week.

“Summary of changes: Add two new arch APIs: getConflictingWireWire and getConflictingPipWire; Major rewrite of router1,” Clifford writes in his pull request to the project. “This new router now uses finer-grain ripups and has no non-ripup phase anymore. It uses arcs as unit of work and always routes the unrouted arc with the worst budget-to-estimate ratio first. This does not yet do timing-based ripups and restarts, but that will be easy to add once this PR is merged.”

A review of the pull request, which merges 20 individual commits, has been requested. Should it be accepted, the changes will be merged into nextpnr’s master branch.

The full pull request can be found on the nextpnr GitHub repository.

David Shah Demos Linux on Mor1kx SoC via End-to-End FOSS Flow

Developer David Shah has published a demonstration of Linux running on a mor1kx-based OpenRisc system-on-chip with 32MB SDRAM, built using a wholly free and open source software (FOSS) workflow.

“Linux on an mor1kx based SoC with 32MB SDRAM built using an end-to-end FOSS flow — FuseSoC, Yosys, nextpnr and Trellis, targeting the ULX3S ECP5 board,” David writes of the project via his Twitter account. “Many thanks to @alt_kia and @OlofKindgren for their help with debugging.”

David’s demo images and videos show the boot process, a “blinky” demo using the Linux “heartbeat” function, and another using the BusyBox shell. David also details a bug which had held the project up, in which Yosys was found to be wiping out of the read ports of the translation lookaside buffer (TLB) — since reported and fixed.

The full demonstration can be found on David’s Twitter account.

OpenWrt Receives RISC-V Port, Targetting HiFive Unleashed, QEMU

Developer Zoltan Herpai has announced a RISC-V port of the embedded-focused OpenWrt Linux distribution, currently targeting the HiFive Unleashed development board and QEMU emulator with additional platforms expected to follow in the coming months.

“I’m happy to announce a port of RISC-V for OpenWrt,” Zoltan explains in his announcement message. “Current status is: based on 4.19 — pull requests and patches for trunk will be sent once support for 4.19 is merged into mainline and core package changes are worked out. Until then, the port is in a staging tree; mainline musl support is expected for musl 1.21, patches are included in the tree for the current 1.20 for testing; currently builds with glibc as default; OpenWrt packages are built regularly on an external buildbot; documentation is added to the wiki.”

The port currently targets the SiFive HiFive Unleashed development board and the QEMU emulator, Zoltan has confirmed. “There are further development boards expected in the next few months,” he adds.

Described as an experimental port — “you won’t be able to run Quake on it yet, sorry,” Zoltan jokes — the new OpenWrt is available in a staging tree of the project’s git repository.

“Fomu” FPGA Board Fits Inside a USB Port, Supports Open Silicon Cores

Tim ‘mithro’ Ansell has shared details of a new FPGA board design, the Tomu FPGA or “Fomu”, which fits entirely inside a standard USB port and which will be funding via Crowd Supply in the near future.

Based on the Lattice iCE40UP5K, with 5,000 lookup tables (LUTs), digital signal processing (DPS) tiles, 128kB RAM, and 1,024kB flash, the board design manages to fit two touch buttons and one RGB LED on a board which slots near-invisibly into any full-size USB port. The design is a variant of Tim’s earlier Tomu microcontroller board, but where its predecessor was hand-solderable the Fomu requires assembly by machine.

“If you want, you can treat the new Fomu (Tomu FPGA) as just a @risc_v CPU device inside your USB port,” Tim writes on Twitter. “Write bare metal C, @ZephyrIoT or even @micropython (thanks to my https://fupy.github.io project) without ever touching Verilog or FPGA design.

“Big thank you to: @TinyFPGA for building the prototypes and proving it was possible. He is the master of tiny FPGA designs! @xobs for being silly enough to do the crowd supply campaign and mass production a second time. @oe1cxw and @fpga_dave for the FOSS toolchain!”

More information is available on the Crowd Supply page, where interested parties can register to be alerted when crowdfunding is opened.

Hex Five, Andes, Gowin Partner on RISC-V MultiZone Security

Hex Five Security has announced a partnership with Andes Technology and Gowin Semiconductor to implement the open MultiZone Security trusted execution environment added to Andes’ N(X)25 RISC-V cores on Gowin’s GW-2A FPGAs — and the three companies have plenty to say about the future of open silicon in China.

“The Chinese market will be the first mass adopter of RISC-V,” claims Andes chief technology officer Dr. Charlie Su. “We’re happy to work with Hex Five to provide our customers a simple, robust security implementation that based on our RISC-V cores and comprehensive AndeSight, an Eclipse-based development environment and optimised toolchains to provide leading performance and reduced development time.”

“Increasingly, customers in China see security as a core requirement of their products,” adds Gowin’s Jim Gao. “With MultiZone Security, they can implement a robust security solution on our existing FPGAs without the need for new hardware, deep security expertise or even any changes to their toolset and workflow. This allows a customer to get to market fast, which is the goal of our FPGA solutions.”

“The cost of a robust security implementation on RISC-V is now negligible — the future of RISC-V is security by default,” concludes Don Barnetson, co-founder of Hex Five Security, referring to the company’s decision to release its MultiZone Security as a free and open standard. “We’re very excited to enter the Chinese market with such strong partners and expand access to simple, robust security that any developer can implement.”

The implementation is being demonstrated this week at the Andes RISC-V Con, the companies have confirmed, while the MultiZone Security standard itself can be freely downloaded from Hex Five’s GitHub repository.

FOSSi News In Brief

• APIO 0.40 released with official support for UP5K boards.
• First RISC-V-based SHAKTI processor to be built wholly in India boots.
• UltraSoC publishes a retrospective of its Bristol RISC-V meet-up.
• China RISC-V Industry Consortium founded for RISC-V promotion, talent cultivation.
• Hackaday publishes “Logic Analysers for FPGAs: A Verilog Odyssey.”
• EU Open Source Observatory (OSOR) praises RISC-V’s opportunity to create “a technical and scientific ecosystem around an open design.”
• David Shah publishes IcySprites Verilog-outputting GIMP plugin proof-of-concept.
• Programming a RISC-V softcore with Ada.
• The Conversation argues open-source hardware could defend against the next generation of hacking.
• Olof Kraigher launches open-source Rust-based VHDL parser and language server project.
• Netronome announces open chiplet architecture to “democratise production of integrated silicon products.”
• CNXSoft details not one but two low-cost Kendryte K210-based development boards.
• Hex Five Security forms strategic advisory board with Celeste Cooper, Jon Geater, and Art Swift.
• Imperas launches free RISC-V Open Virtual Platform Simulator riscvOVPsim.
• Linux developer Arnd Bergmann sees RISC-V “killing off any of the minor licensable instruction set projects, just like ARM has mostly killed off the custom vendor-specific instruction
  sets already.”

Have feedback or news for inclusion in a future newsletter? Please send this to ecl@librecores.org. Subscribe to get El Correo Libre direct to your inbox.