Analog Interface of Optical Processors
In previous blogs, we detailed how artificial intelligence algorithms run efficiently in our nanophotonics processing units. In this blog, we explore the analog interface needed between these optical cores and the digital world. As we explained in previous blogs, the optical processor performs general matrix multiplication. There are three groups of elements in the multiplication equation, namely input vector, weights, and output vector.
The figure below shows a matrix multiplication (a), its block diagram (b), and implementation using optical and analog systems (c). The value of each element in the input vector and weight matrix needs to be converted into the analog domain, which can be implemented by digital-to-analog converters (DAC). The number of bits in each DAC determine the precision of the corresponding vector or matrix element.
Optical core drives an array of photodiodes (PDs). The currents generated by these photodiodes are amplified by an array of transimpedance amplifiers (TIAs) and then converted into the digital domain by an array of analog-to-digital converters (ADCs). The number of bits in each ADC determine the precision of the output vector.
In this blog, we will go over the operation principles and performance parameters of these analog blocks.
High-speed medium-precision DACs
A digital-to-analog converter is an electronic circuit that converts a multi-bit digital signal into an analog signal with multiple levels as shown in the below picture (a). Resolution, maximum operation frequency, settling time, and power consumption are the main performance parameters of a DAC. In a linear binary-weighted DAC, an N-bit digital input corresponds to 2^N equally separated analog levels at the output. 2^N is the dynamic range of this DAC, as it is the ratio of the biggest possible step and the smallest step at the output. Deviation from the ideal transfer function is quantified with integral nonlinearity (INL) and differential nonlinearity (DNL) as shown below (b). If the DNL is smaller than the least significant bit (LSB) step size, the DAC becomes monotonic, which means that with the increasing digital input code, the output can only increase.
In general, a linear, monotonic, high-resolution DAC dissipates a lot of power and occupies a large silicon area. In our artificial intelligence applications, we adopted mid-resolution DACs for optimum performance, as they can run at very high speed, driving the optical core with high bandwidth, while still being power efficient.
Amplification of photodiode current
Photodiodes have high-speed current outputs. These currents are converted into the voltage domain by transimpedance amplifiers (TIAs). For the given power consumption, there is a trade off between dynamic range and bandwidth of the TIA. The TIA needs to have a very high bandwidth to leverage the high performance available in the optical domain. To meet the high bandwidth requirement, the feedback resistor (shown as R in the picture below) cannot be very large. As R is also equal to the gain of the TIA, to achieve rail-to-rail swing at the final output, an additional voltage gain stage is needed after the TIA. This final output signal is sampled and converted into the digital domain by the ADC.
High-speed medium-precision ADCs
An analog-to-digital converter is an electronic circuit that converts analog signals into digital signals as shown in the below picture. First, the analog input is sampled and held on an internal capacitor. Next it is quantized into a digital signal after multiple comparison steps. The real resolution, which is known as ENOB (effective number of bits) including high-speed and nonlinear effects, maximum sampling frequency, and power consumption are the main performance parameters of an ADC.
One of the benchmarks for ADCs is the Walden figure of merit (FOMW) shown in below equation, where P is power consumption, f_S,Nyq is the Nyquist sampling frequency.
The picture below shows the FOMW of all the ADCs published in the two main integrated circuits conferences in the last two decades. This graph suggests that to double the sampling frequency of an ADC on the state-of-the-art envelope, you need to quadruple the power consumption. From the equation we can see that for each additional bit (for example if you increase ENOB from 9 to 10, or from 11 to 12) you need to double the power consumption.
This implies a high-cost design space for high-speed mid-resolution ADCs needed by artificial intelligence applications. However, this state-of-the-art boundary moves down each year, as many of the most efficient ADCs were designed in the last couple of years. The reason for this positive trend is the availability of higher-speed process nodes and new circuit design techniques, such as novel ADC topologies and new amplifier designs used within the ADCs. Here, at Lightmatter, we are applying multiple of these new methods to develop power efficient, high-speed, mid-resolution ADCs that can digitize the high bandwidth outputs from the optical core without adding a significant power overhead to the total power consumption of the chip. This efficiency rule also applies to our DAC and TIA designs.
