High Level Synthesis in VLSI
With the advancements in the digital electronic technologies and devices that are integrating System-on-chip (SoCs), the design complexity of hardware is also increasing.
The designing of hardware systems is thus being optimised with various methodologies and tools that can produce the design output with reliability and efficiency.
Levels of abstraction :
Hardware design can be implemented through various levels of abstraction, or operational levels. Most commonly utilised levels of abstraction are the gate level, register-transistor level (RTL) and algorithmic level.
In software design, as the program complexity and size grew, it became necessary over a period of time to shift from translators assemblers to compilers, that is, move to higher levels of abstraction to simplify the process of design.
Similarly, automated hardware synthesis tools were developed due to the translation from higher levels of abstraction for software. Hardware circuits were able to be produced automatically synthesizing an easier description of the required circuit. This automation gave rise to the concept of logic synthesis and high level synthesis.
About High Level Synthesis :
While logic synthesis operates with the RTL description of the design, high level synthesis works at a higher level of abstraction, the algorithmic level. High-level Synthesis (HLS) can be defined as the translation from a behavioural description of the intended hardware circuit into a structural description similar to the compilation of higher programming languages like C, C++ into hardware description languages like Verilog or VHDL. HLS acts as the next step in design automation, succeeding logic synthesis.
The objective of HLS is to extract parallelism from the input description, and construct a micro architecture that is faster and cheaper than simply executing the input description as a program on a processor.
The input to HLS involves a set of constraints or rules that are set by the designer in order to achieve RTL synthesis.
The output of this High Level Synthesis can include the following:
RTL Implementation : It includes the RTL netlist which contains all the libraries, parameter specifications, control logic and so on.
Analysis Feedback : It includes the reports on the performance of the synthesis.
Design steps involved in high level synthesis :
The following tasks are executed by HLS tools :
1. Compiling the specification : involves code optimization
2. Allocating the hardware resources, may it be the storage components or the buses or the ICs : defines the type and number of hardware resources
3. Scheduling the operations : operations are scheduled in cycles
4. Binding the scheduled operations to their functional units
5. Binding the variables to the storage elements
Generating the RTL architecture : Once allocation, scheduling and binding are done, all the design decisions generate an RTL model.
The tasks are managed in a sequential manner which manages the complete computational complexity of the synthesis.
How is it beneficial?
As compared to logic synthesis which occurs at the RTL, high level synthesis provides a faster and high-quality path and enhancing the design productivity.
The benefits that HLS provides are derived from the fact that it operates at a higher level of abstraction with high level languages :
1. It easily evaluates algorithmic changes.
2. It can explore multiple architectures while focusing on the designing of core functionalities.
3. It can easily debug and test functionality of the input descriptions.
The utilization of HLS however depends majorly on whether the micro architecture given can be satisfied with designing in RTL or if different algorithms and architectures can be explored to experiment under a variety of constraints. There have been multiple areas that have benefitted from HLS like automation industries, image processing, FPGA based applications and so on.
References :
- An Introduction to High-Level Synthesis, Philippe Coussy, Michael Meredith, Daniel D. Gajski, Andres Takach
- High-level Synthesis, Issam W. Damaj, Dhofar University
- Understanding high-level synthesis design’s advantages, By John Sanguinetti Chief Technology Officer Forte Design Systems Inc.
- Machine Learning for Electronic Design Automation: A Survey
