SystemVerilog

SystemVerilog is standardized as IEEE 1800. SystemVerilog is based on Verilog and some extensions. Verilog-1995 and -2001 limit reg variables to behavioral statements such as RTL code. SystemVerilog extends the reg type so it can be driven by a single driver such as gate or module. SystemVerilog names this type “logic” to remind users that it has this extra capability and is not a hardware register.
SystemVerilog for register-transfer level (RTL) design is an extension of Verilog-2005; all features of that language are available in SystemVerilog. Therefore, Verilog is a subset of SystemVerilog.
SystemVerilog for verification uses extensive object-oriented programming techniques and is more closely related to Java than Verilog. These constructs are generally not synthesizable.
in addition to the new features above, SystemVerilog enhances the usability of Verilog’s existing language features. The following are some of these enhancements:
• The procedural assignment operators (<=, =) can now operate directly on arrays.
• Port (inout, input, output) definitions are now expanded to support a wider variety of data types: struct, enum, real, and multi-dimensional types are supported.
• The for loop construct now allows automatic variable declaration inside the for statement. Loop flow control is improved by the continue and break statements.
• SystemVerilog adds a do/while loop to the while loop construct.