ICLAB Lab09 Note

Week 11

LAB Description

Topic of this week

1. Introduction to SystemVerilog
2. Design Using SystemVerilog
3. Verification Using SystemVerilog

Design

Happy Farm (HF)

Description

Build a well-known game called Happy Farm with several operations and different crops in SystemVerilog.

GitHub

2021_Spring_NCTU_ICLAB/Lab09/

What did I learn?

1. Basic of SystemVerilog.
2. Different usage of SystemVerilog from Verilog.
3. Different specs may result in different performance with same design.

SystemVerilog Note

SystemVerilog is a Hardware Description and Verification Language based on Verilog. It has features inherited from Verilog, VHDL, C, C++, and it aims to solve the gap between circuit complexity and human productivity.

Compared to Verilog, SystemVerilog has higher abstraction, and has more advanced verification techniques (ex: OOP). It is both design/verification languanges, which improves communication between design team and verification team.

Overview of SystemVerilog

Packed vs Unpacked Array

• Packed Array (Vector width in Verilog-2001) : the dimensions declared before the object name.
• Unpacked Array : the dimensions declared after the object name.

Typedef

• User Defined Type (UDT)

Enumerate

• Provides built-in assertion.
• Data type defaults to 31-bit, signed int.

Structure

• Enhance readability.

Union

• Allows a single piece of storage to be represented with different ways using different named member types.

Package

• To share UDT across multiple modules.

Class & Randomization

• SystemVerilog pre_randomize & post_randomize

Q & A

Q : Weird or unreasonable bugs during 03_GATE simulation.
A : Make sure 03_GATE have eaten the .sdf file correctly.

I had a mysterious bug during 03_GATE simulatioin in this lab. As the picture shows, I’ve reset all the registers bug there was a particular register id[3] wasn’t reset. It did not make any sense.

Unreasonable unknown signal after reset.

It turned out that the Standard Delay Format (SDF) files generated by 02_SYM, whose paths were specified by Tool Command Language (TCL) files, did not match the paths specified in TESTBED.sv.

Check two paths match or are linked to each other.

1. TESETBED.sv sdf_annotate("path_of_sdf_file_for_simulation", IN_OUT);

2. syn.tcl write_sdf [options] path_of_generated_sdf_file

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