Computer Architecture — Pipeline

Intel’s Coffee Lake Hexa Core Desktop Processor Die Analysis

The above photo is Intel’s Coffee Lake 6-core desktop processor. From the Intel’s website, we can find more detailed information about this processor, it has 6 cores, level-1 cache 64 KiB per core, level-2 cache 256 KiB per core, level-3 cache up to 16MiB(shared), its instruction and architecture is x86–64. Before I took this course (CPEN 411, offered by UBC ECE), I only know very basic concepts, for example, ‘more CPU cores = more computing units = better performance’, in my later posts, I will explain each variable a bit deeper as well as the simulation implementation.

Topic 1: Pipeline

Remember one thing -> Software can be smart, but processor might be stupid

5-stage RISC Illustration: from left to right, Fetch(F)->Decode(D)->Execute(X)->Memory(M)->WriteBack(W)

The above graph shows a Reduced Instruction Set Computer (RISC) architecture. Instructions go from left to right, stage by stage, assuming each stage only take one cycle, then from left to right, one instruction needs 5 cycles to be finished.

Summary of Each Stage

Fetch Stage (F): Fetch the next instruction from the memory, at this time the instruction is encoded.