Introduction to Digital VLSI Design
=====System Specification=====
1. System Specification
According to product requirements of market opportunity, customer needs, feasibility, identify the product specs and functionality
#####Frontend#####
=====Architectural or System Level Design=====
2. Functional/ Architecture Design or System Level Design
According to spec requirement, create or purchase the intellectual property (IP) blocks, and defining the software interfaces, timing, performance, area, and power constraints.
3–1. Architecture Verification
Building a application software using high-level language like C, C++, or SystemC to evaluate or verify architecture, performance, and power of the entire system.
3–2. Formal Verification — Property Checking
To prove that the implemented system model meets the design requirements (or specifications).
=====Functional Design and Logic Design=====
4. Behavior Synthesis and Register Transfer Level (RTL) design
Implement the functional models in a hardware description language (VHDL, Verilog). Functional verification is also performed to ensure the RTL design is done according to the specifications.
5–1. Functional Simulation (verification by simulation)
To reduce functionality bugs, a separate hardware verification group will take the RTL and design testbenches and systems to check that the RTL actually is performing the same steps under many different conditions, classified as the domain of functional verification. This does not consider the timing delays of the design elements.
It verifies the IC level connectivity, IP blocks in the IC-level environment (generally, IP blocks are pre-verified), end-to-end functional paths, pad connectivity, inter-module interaction, external module interaction, and so on.
The testbench is a set of codes that check whether the RTL implementation meets the design specification.
5–2. Formal Verification
To prove the functional equivalence of a design by comparing it with the golden design
5–3. Emulation
5–4. FPGA-Based Prototyping
=====Circuit Design=====
6. Logic synthesis & Gate level
Convert the hardware description (RTL) into a design implementation in terms of logic gates (netlist) given a technology library and timing constraints. This process takes power, speed, size into consideration. To verify whether the synthesis tool has correctly generated the gate-level netlist, a verification should be done.
7. Design for Testing (DFT)
#####Backend#####
=====Physical Design and Verification=====
7. Layout level or Mask level
Gate level netlist is converted to a complete physical geometric representation. The output file of the layout is the GDSII used by the foundry to fabricate the chip.
- Design Netlist (after synthesis)
- Partitioning
- Floorplanning
- Placement
- Clock-tree Synthesis (CTS)
- Routing
- Dummy Metal Filling
- Physical Verification (DRC)
- RC-extraction, Timing Analysis, SI Analysis (STA)
- Formal Verification (LVS)
