Making semiconductors dense and cool


Crowded places get hot, and few compare to the inside of a semiconductor, with its multiple levels, 3D metal interconnects, and dense components packed tightly in a small space. If you imagine the soon-coming 3D vertical metal interconnects in the sub-micron range as people — and the dense chip/package as a small, one-square-meter elevator — there would be around 100 trillion people inside the lift.

The packed house inside a semiconductor package is due to users clamoring for these faster, more powerful chips to handle things like AI, cloud, data centers, other advanced computational applications, and today’s insatiable consumer demands for content.

All those applications require high bandwidth, low delay, and low power dissipation. For data-intensive high-performance applications — such as high-performance graphics accelerators, network devices, high-performance datacenter application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs) — one of the main challenges is the memory “wall.” This refers to the growing speed disparity between the central processing unit (CPU) and the memory outside the CPU chip, due to the long interconnect length between the two.

3D-stacking memory-on-logic can accelerate the chip-to-chip communication. Fine-pitch, high-density 3D interconnect technologies are needed to support orders-of-magnitude energy and execution time improvements for future 3D memory-on-logic architecture.

For example, so-called “monolithic 3D integration,” using nanoscale interlayer vias (metallized holes that connect different layers), enables multiple layers of transistors and memory cells to be deposited sequentially — vertically, on top of one another — and connected by short, high-density interlayer vias during semiconductor manufacturing. Another advanced packaging technology, “heterogeneous 3D integration,” enabling each thin device layer to be fabricated separately and then stacked vertically, also has great potential to further improve the vertical metal interconnects’ density as well as system performance and bandwidth.

Yet as we push the envelope with these ever-increasing interconnect densities, the challenges mount not only in the semiconductor fabrication processes, but also on the thermal management front, where 3D integration leads to both higher temperatures and more difficulties in removing the heat due to strong thermal coupling between the components in the 3D stack.

These conditions can lead to lower performance, as well as permanent failures from electromigration, melting, and plastic deformation. And handheld devices can simply get too hot to handle.

Conventional liquid cooling solutions no longer are sufficient. Alternative advanced liquid cooling solutions, such as delivering the liquid coolant inside the 3D die stacking layers, have been proposed, but they are not compatible with the requirements for high-bandwidth communication between different tiers of a 3D system.

Our solution is direct liquid jet impingement cooling on top of the 3D die stack combined with system partitioning technologies. Manufactured using low-cost polymer fabrication techniques, the solution provides an efficient cooling method in which the liquid coolant is directly ejected from nozzles on the chip backside. This results in high cooling efficiency due to the absence of thermal interface material and temperature gradients across the chip surface. Surface engineering enhancement methods, including microporous structures, micropillars, thermal vias and microchannels, are developed in our lab to further improve the jet cooling efficiency.

Surface engineering enhancement for impingement jet cooling with alternating inlet and outlet jets: (a) concept of direct jet cooling on silicon chip; (b) microscale copper wire array; (c) nanoscale copper wire forests; and (d) and (e) metal-based porous structures. (Illustration by Purdue University/Alpha Lab in collaboration with Stanford NanoHeat lab)

There are still hurdles to overcome. Many parameters of the cooler design are very complex. Other challenges include the integration of cooling solutions into the semiconductor packaging manufacturing process; thermomechanical reliability of the cooling solutions on the chip; and compatibility of the cooler materials with the semiconductor packaging materials.

Novel cooling strategies can enable more powerful semiconductors with higher interconnect densities to achieve much faster computational performance in order to power the devices and systems that advance the modern world. These technologies will pack much more functionality into smaller, faster, more potent packages; use less power; and reduce costs.

The goal of my research lab — Alpha Lab (All-in-one for Semiconductor Packaging, Heat transfer, and Assembly Lab) — is to steer semiconductor packaging technology into a more efficient, reliable space and unlock the potential for nanotechnologies to benefit humankind.

Tiwei Wei, PhD

Assistant Professor of Mechanical Engineering

Principal Investigator, Alpha Lab (All-in-one for Semiconductor Packaging, Heat transfer, and Assembly Lab)

School of Mechanical Engineering

Birck Nanotechnology Center

College of Engineering

Purdue University