Better quantum chips

By Matt Reagor, Director of Engineering

Building quantum computers that surpass the capabilities of classical computers requires not just more qubits, but better qubits. To perform longer and more complex computations, we need qubits to stay in a quantum state as long as possible without losing energy to their environment. The way we fabricate superconducting quantum circuits plays an important role in qubit performance.

Our fab process has hundreds of steps and dozens of components and materials, making it hard to distinguish whether and how small variations in the process contribute to individual qubit performance. In the largest study of its kind, we evaluated specific combinations of manufacturing processes using 150 qubits. Today we’re sharing our results describing an end-to-end series of optimizations that produced qubits with functional lifetimes as high as 110μs. These improvements will be integrated into our QCS platform in the coming months.

Optimizing interfaces

When amorphous materials cool to near absolute zero temperatures, their disorder allows for nanoscopic pockets of electrical charge to get frozen in. Surfaces and interfaces between materials on devices tend to host these amorphous traps. How many of these traps form is largely determined by the fabrication steps used to make the device.

Tiny amounts of noise are generated when these pockets charge and discharge. It turns out that superconducting qubits are sensitive enough to detect these events. In fact, these switching traps (“two-level systems”) have been shown to be a leading source of decoherence. We show in this work that integrating fabrication improvements for three key device interfaces yields substantially better qubits.

Substrate-metal interface

Superconducting qubits are made on insulating (silicon) wafers. The region where the superconducting metal of a qubit sits on the silicon defines the substrate-metal interface. This region is amorphous and a source of noise for qubits. Removing oxide from the silicon surface before metal deposition has been shown to reduce the amorphous layer between metal and silicon, resulting in better superconducting resonators and recently, qubits. Our new results quantify the improvement associated with this technique across many qubits (improving from 40 μs to 70 μs), and moreover, we show that this technique is compatible with other interface improvements.

Device-air interfaces

The top surface of metal-silicon chips can also host metal oxides and silicon oxides that are difficult to control. The microscopic structure of these surfaces can play a role in the amount of noise that’s trapped. To understand these effects, we fabricated qubits under different reactive ion etch conditions. We correlated cross-sectional profile images from scanning-electron microscopes to noise levels, and found that removing roughness from these surfaces can account for T1 improvements from 30 μs to 70 μs.

Metal-metal interface

Integrating Josephson junctions (the nonlinear elements that make qubits interesting) into our superconducting qubits requires connecting two metal layers together (a metal-metal interface). To investigate this loss channel, we establish connection between aluminum and niobium using two primary approaches. In the first method, we vary the dimension of an Al metal layer that overlays Nb. In the second method, a second electron beam lithography step exposes a small area at the Al-Nb border where an in situ ion milling step at high power removes the Nb oxide before the deposition of an Al bandage layer. While the relative merit of these two approaches have been debated, our study directly compares them. We find that both can be optimized to reach similar values (T1 = 70 ± 22 μs and T1 = 76 ± 13 μs, respectively).

Results

These average decay times are ~4x longer than those demonstrated on our previous 19Q-Acorn chip, with the best qubits showing T1>100μs. Applying this framework to modules beyond this study could result in lower noise solid state quantum computers in the future.

Conclusion

While our quantum chips benefit from decades of silicon manufacturing insights and techniques, two things at Rigetti made it possible for our team to approach silicon manufacturing R&D for quantum devices in a new way. First, we have the only captive solid state qubit foundry, Fab-1. Fab-1 (and the deep technical expertise of the engineers who run it) allows us to quickly explore new manufacturing concepts on real silicon. Equally important, Rigetti has also built the world’s most advanced quantum software stack. Device characterization here is now largely automated, which our R&D teams leverage to test ideas at scale.

Fab-1 and Rigetti’s test infrastructure made it possible for us to show, for the first time, that silicon processing techniques can be optimized in an end-to-end manufacturing process. With enough statistics (roughly 150 qubits reported in the experiment), we were able to quantify the effect of each improvement directly.

We’re now working to incorporate the insights from this work into our production processes, and continuing to investigate further optimizations to accelerate the pursuit of low-noise quantum computers.


A. Nersisyan, S. Poletto, N. Alidoust, R. Manenti, et al (2019). “Manufacturing low dissipation superconducting quantum processors”. https://arxiv.org/abs/1901.08042