Gain deeper control of Rigetti quantum processors with Quil-T
By Alex Hill, Senior Quantum Systems Engineer
Today’s quantum computers rely on careful measurements of hundreds of parameters that can vary over time. Take the humble X gate: to flip a qubit from the |0> to the |1> state, we have to know the qubit transition frequency and the optimal duration for a gate pulse (the “Rabi Flop”). If the pulse amplitude, time, or frequency are incorrect, then the X pulse will no longer exactly produce the intended gate, resulting in errors. We call the set of parameters that define all of the gates calibrations.
These calibrations are especially important for superconducting qubit architectures, as the physics of transmon qubits is very rich and can open a number of ways of performing the same gate. In the case of the X pulse, there are a number of pulse shapes (Flat Pulses, Gaussian Pulses, etc.) that more or less accomplish the same task; however, the usefulness of each of these pulse shapes depends on the pulse’s ability to minimize a wide variety of errors, for example, accidental transitions to the transmon’s |2> state, also called “leakage.” Clever design of pulse shaping can dramatically improve the error rate of both single-qubit and two-qubit quantum gates. Until now, these manipulations were hidden from view.
Today we’re releasing Quil-T™, making gate definitions and pulse parameters completely editable across the entire Rigetti Aspen-8 processor. This gives Rigetti QCS users more fine-grained control over the parameters used to enact every gate operation, unlocking the ability to experiment with optimal control, control precise pulse timing, and construct novel gate schemes that can dramatically reduce overall gate depth. In the coming months, pulse level control functionality leveraging Quil-T will be available to more users through Amazon Braket.
How does this work in practice?
Quil-T introduces a new language extension to QUIL, Rigetti’s quantum instruction language, that augments normal QUIL programs with user-defined calibrations. Let’s look at an example:
DECLARE ro BIT[1]
RX(pi) 0
MEASURE 0 ro[0]This program flips the qubit into the |1> state and records the result. Previously, the physics underpinning each of these operations was abstracted away, allowing us to focus on developing new algorithms.
Now, Quil-T allows you to view and edit the definition of each of these instructions using the existing pyQuil interface to QUIL:
from pyquil import get_qc
import numpy as np
qc = get_qc()
cals = qc.compiler.get_calibration_program()
rx_cal = cals.get_calibration(RX(np.pi, 0))
print(rx_cal)Outputs:
DEFCAL RX(pi) 0:
FENCE 0
NONBLOCKING PULSE 0 “rf” drag_gaussian(duration: 1.3999999999999998e-07, fwhm: 3.4999999999999996e-08, t0: 6.999999999999999e-08, anh: -190000000.0, alpha: 0.2930202880917037, scale: 0.735768304830665, phase: 0.0, detuning: 0)
FENCE 0Compilation of QUIL programs can be split into two steps: translation from a standard QUIL or pyQuil program to native QPU instructions, and a final step converting these native instructions into an executable binary. Before the last step, the compiler substitutes the calibration represented by this DEFCAL statement for the X gate on qubit 0. What follows the DEFCAL statement is a list of pulse-level instructions that control the timing and parameters of a sequence of pulses. The first operation, FENCE 0, tells the compiler to make sure that no other operations can be applied to qubit 0 during the operation of this pulse program.
Let’s say we wanted to compile our program using a new version of RX(pi) that uses an amplitude of 0.5 (arbitrary units, but in this case we can call them “Volts”). Our final program would look something like this:
DEFCAL RX(pi) 0:
FENCE 0
NONBLOCKING PULSE 0 “rf” drag_gaussian(duration: 1.3999999999999998e-07, fwhm: 3.4999999999999996e-08, t0: 6.999999999999999e-08, anh: -190000000.0, alpha: 0.2930202880917037, scale: 0.5, phase: 0.0, detuning: 0)
FENCE 0
DECLARE ro BIT[1]
RX(pi) 0
MEASURE 11 ro[0]Here, the compiler checks to see what calibrations are included with your program. If there’s a match between a provided calibration and a gate in your program, the compiler will override the default calibration with your own definition.
The pulse, defined by NONBLOCKING PULSE 0 “rf” drag_gaussian(), represents a physical pulse playing on the RF drive line for the qubit (defined by “rf”). drag_gaussian() specifies that the pulse should use a waveform with a Gaussian shape, modulated by an additional phase.
We can see some of the ingredients for a successful X gate: a pulse time (drag_gaussian->t0) and a pulse amplitude (drag_gaussian->scale). But what about frequency?
The qubit frequency is hiding in the definition “rf”, which defines the frame over which the pulse should play. Quil-T introduces a few new QUIL terms that allow for the manipulation of gate parameters:
DEFCAL → create new calibrations and pulse programs
DEFFRAME → manipulate definitions of frames (for example, the frame of precession of the qubit) on which waveforms “play”
DEFWAVEFORM → change how the frames should be manipulated (for example, using a Gaussian envelope)
All of these can be redefined in a QUIL program, either directly or via the pyQuil interface.
Quil-T also allows users to explore the underlying physics of our superconducting qubits by unlocking high-resolution timing control. Standard experiments in quantum physics, like measuring the frequency of a qubit using Ramsey spectroscopy, are expressible as simple QUIL programs:
# Set up the T2 experiment!
delay = 100e-9
detuning = 5e6 # Hz
phase = -detuning * delay * 2 * np.pi
prog = Program(f”””
DECLARE ro BIT
RX(pi/2) 33
DELAY 33 {delay}
RZ({phase}) 33
RX(-pi/2) 33
MEASURE 33 ro
“””)Sweeping the delay time and plotting the output of this program:
How can Quil-T help algorithms researchers?
Enforce precise program timing
QUIL provides a great deal of control over compilation, and Quil-T takes this a step further by unlocking the ability to enforce the sequencing and timing of the underlying gate programs. By default, two-qubit gates compiled through the Rigetti stack fence all qubits, meaning that two-qubit gates must be run in isolation:
DEFCAL CZ 32 33:
FENCE
NONBLOCKING PULSE 32 33 “cz” q32_q33_cz/CZ
FENCE…
This default behavior is chosen to reduce the probability of unwanted qubit-level effects like crosstalk. However, this comes at the expense of overall circuit time. For complex algorithms, the increase in circuit depth may be significant enough to outweigh any potential effects of crosstalk. With Quil-T, the default global fence on two-qubit gates can be removed by modifying the FENCE instructions to include only qubits directly involved in the operation:
DEFCAL CZ 32 33:
FENCE 32 33
NONBLOCKING PULSE 32 33 “cz” q32_q33_cz/CZ
FENCE 32 33…
The compiler automatically reschedules CZ programs to use the new timing. Quil-T allows almost complete control over program scheduling.
Reducing circuit depth with customized gate sets
As we’ve already seen, CZ gates produce a controlled phase flip in a target qubit using a single pulse applied to the source qubit; however, this phase flip is fixed to a single phase of π. CZ can be generalized to a continuous family of gates, called UZZ or CPHASE gates, which apply a controlled phase of arbitrary size. Using Quil-T, we can construct arbitrary pulse programs, including CPHASE, that leverage existing gate parameters.
DEFCAL CPHASE(%theta) 32 33:
FENCE 32 33
NONBLOCKING PULSE 32 33 “cphase” q32_q33_cphase/sqrtCPHASE
SHIFT-PHASE 32 33 “cphase” 3.041220623789862 + -0.5*%theta
NONBLOCKING PULSE 32 33 “cphase” q32_q33_cphase/sqrtCPHASE
SHIFT-PHASE 32 33 “cphase” -1*(3.041220623789862 + -0.5*%theta)…
Here, we’ve constructed a new pulse program, CPHASE(%theta), that plays two waveforms, q32_q33_cphase/sqrtCPHASE, with a phase shift between them. While these new waveforms are provided in Quil-T by default, we could calibrate them ourselves by finding a pulse that provides roughly half the interaction time of the full CZ. Quil-T allows for parameterized calibrations, so we can construct a gate that is a native implementation of CPHASE.
This new gate can be used to dramatically reduce the number of gates required to construct native circuits that rely on arbitrary two-qubit phase shifts. As a quick example, one standard decomposition of CPHASE(pi/3) using pure CZ gates and single-qubit rotations produces the following native implementation:
RZ(-pi/2) 33
RX(pi/2) 33
CZ 33 32
RX(pi/2) 33
RZ(pi/4) 33
RX(-pi/2) 33
CZ 33 32
RZ(pi/4) 32
RX(-pi/2) 33
RZ(3*pi/4) 33With a native CPHASE, we eliminate all of the single-qubit rotations and 50% of the two-qubit operations. To guide pulse construction and algorithm development, CPHASE pulses are automatically provided using Quil-T wherever CZ pulses are available.
Design and test new optimal control algorithms
As we saw earlier, Quil-T users can specify almost every attribute of the pulses that generate both single- and two-qubit gates. This can be done at a high level using parameterized waveform templates (like drag_gaussian), or by manipulating individual waveform envelope samples of the pulses themselves.
This new feature set empowers Rigetti collaborators like Q-CTRL to apply their expertise in pulse-level control on a real-world NISQ system. Their work has the potential to significantly improve algorithmic performance and hardware stability in quantum processors through the generation and execution of new optimized definitions of the gates used to enact quantum logic. These new gate sets perform well even in the presence of the various sources of noise that are endemic to real quantum computers, such as amplitude drift and dephasing.
Read more from Q-CTRL: Building infrastructure software to support the future of cloud quantum computing with Rigetti Quil-T
The quantum computing community is moving rapidly, and there is an entire constellation of optimal control protocols in development. Quil-T allows researchers to take the standard QPU calibrations a step further and optimize their NISQ-era algorithms at the pulse level across our full Aspen-8 quantum processor, enabling the exploration of custom-built circuits with higher fidelities and lower depths than native implementations can allow.
