The end of Moore law and the solution proposed

The end of the increasing of transistor performance through the technology and presentation of asynchronous electronic, a promising technique

Introduction

Since 70s the diminution of the transistor size has gone hand in hand with the increasing of the performance and the reduction of power consumption. Since few years, transistor downsizing is always possible, but the increase of the performance isn’t correlated any more with the decrease of energy consumption [1]. The increasing efficiency is more and more difficult to reach when transistors are coming smaller and smaller. In the first part we will speak about the physical limitations when transistors become more and more small and the end of Moore’s law. To compensate the lack of new transistor technologie performances, it is imperative to find another way if we want to continue the technical advance. In the second part we tackle a promising solution but it has been abandoned despite the many researches made.

The end of More law

Since decades the end of Moore’s Law is predicted, this law involves a doubling of the transistor number into processors and a significatif increase of its efficiency every two years. Since 2004 the frequency of processors hasn’t increased, this is due to the heat density becoming more and more difficult to evacuate [2]. Today another physical limit is reached, the end of the energy efficiency increasing by the reduction of transistor size [1]. The size of one technology is defined by the smallest length between the drain and the source of transistors. “ It is always possible to increase the transistor number by 50% into classic processors like Intel wants to do, but the profit will be only 10%” [3]. With the end of the increase of transistor efficiency, it is possible to be worried about a potential economic crisis in the semis-conductor domain [4]. There is no interest in changing our computer if there are no more benefits. The final limit for the reduction of transistors size is the atom size (0.3nm). Before reaching this size, many quantum effects appear for technologies which come nearer nanometers and become more and more pronounced with the size reduction. For example, below 3nm the tunnel effect is so pronounced that transistors are always open [5].

The diminution of transistor size involves many physic issues. Plenty of compromise should be done to have good performance in speed and in power consumption. Now, we present to you some problems that appear when the size of a transistor becomes smaller and smaller. For small transistors it is necessary to decrease the size of the insolation at the gate level to have quite good performance, this means that the leakage current is drastically increasing. On the other hand, with the reverse short channel effect, the increasing doping which is necessary with the diminution of technologie size implies the increasing of threshold voltage. The increasing of this voltage involves the increasing of power supply to keep the same performances. When the supply voltage is increased, the power consumption is worse. Another effect “punch-through” is the cause of the difficulty to control the current crossing transistors, because the drain and the source of transistors are too near. Plenty of other physic effects make more and more complex the realization, the reproducibility and the reliability of transistors in diminuing the their size [6][7][8].

Difficulties of fabrication imply a vast increase in the production costs, you can see below the price for the different size of FinFET technology [9].

The 5 nm technologie exit since 2020, however no miner has been realized yet with this technologie, the most efficient miner is designed in 7nm. in 5nm technologie no miner is provide for now, but some miners in 5nm are expected. Into the crypto world many anoncement are made, but the only thing that counts is the result . When the technologie size becomes smaller and smaller, the design is more and more difficult, especially for the

realization of a full custom ASIC miner. The limit of the physics implies that the increase of transistor efficiency is more and more difficult. The increase of the performance by a few percent is probably possible but how many billion or tens of billions should be used to reach this result ?

Too focused to reduce the size of transistors again and again, many overly creative techniques have not yet been developed by industries deemed too complex or uncertain. “The end of Moore’s law could be the best thing that has happened to computing in decades. It will force those who build computers to be more creative, to explore new realms in computer science and try out different architectures, circuits, device concepts, physics, and materials, and to look for new computational paradigms from biology and elsewhere” [11]. In the following part we will talk about one of these techniques, promising, known and studied since decades.

The asynchronous, a promising alternative

The asynchronous electronic is a promising solution theorized since the 50s [12], contrary to synchronous electronics it doesn’t have a global clock. This technique has many advantages, it is more efficient in energy, faster, produces less electromagnetic noises or definitely solves the problem of clock synchronization.

In changing the synchronous electronics by asynchronous electronics, in realizing the same fonction, every scientific articles are unanimous, each one said there is a reduction of power consumption. For example, an application of “ pager decoder” the reduction of consumption can be divided by four [13]. For the realization of a DSP, the energy consumption improvement is 47% [14]. On average the energetic performance reaches 30% with very interesting efficiency and in some circuits can be two times faster [15].

The overclocking is a technique used to accelarad functions of circuit, the harate (for an ASIC miner) in increasing the clock frequency. The major problem is if the logic gate inside the circuit misses a cycle, the circuit is totally inoperant. This problem can appear when the clock frequency is too high. To reduce the power consumption, the voltage can be reduced, the clock frequency also because the gates into the circuite are being less quick with the reduction of the voltage. If the circuit doesn’t have a global clock, each part of the circuit goes to the maximal speed, The speed is dependent on the doping concentration which depends on the manufacturing. The variation of doping is always different in different parts of the chip, indeed the speed too. In using an asynchronous miner, when we adjust the

voltage supply, the hashrate is adapted. Many articles highlight the acceleration of circuits in using the asynchronous electronic rather than synchronous electronic. For example the circuit shown in this reference [16], has a speed multiplied by two, a reduction of power consumption and of its area in using asynchronous electronics, in having the same application that the equivalent circuit in synchronous electronics. The increase of speed is not systematic, it is dependent on application and the design objective. The area used for an asynchronous circuit can also vary, it can be bigger or smaller than classic architecture.

Another advantage of the asynchronous electronics is the noise and electromagnetics rayoning reduction generated by digital circuits. The clock and the transition of the logical gate is the main source of the noise in electronic circuits. In asynchronous electronics there is no clock and transitions are not simultaneous, which reduces the associated noise [17][18]. The electric noise and electromagnetic perturbation disturb the analog function in mixt circuits [15]. The asynchronous electronics allows the reduction of the analog electronics consumption by an indirect way in a mixt circuit.

The clock in a synchronous electronic circuit must be global and exactly the same in the entirety of the circuit. If there is a delay superior at 10% of the clock period, this chip can be totally unusable. On a large circuit, the delay of clock propagation can be superior to its wavelength. To avoid this problem and have perfect timing everywhere on the chips in taking the variation of speed, softwares synthesizes a tree clock. The creation of this clock tree is a complex problem which is solved by algorithms and powerful computers [19]. This tree is also a huge source of power dissipation.

Asynchronous circuits shown in previous articles previously cited are for the goal to reproduce the same function made with the equivalent circuits made in synchronous electronics. The electronic designs using asynchronous electronics is clearly not common, but for few niche applications where asynchronous electronics are used their advantages are huge. When scientifics are creative and not only copy previous devices, they have found many ingenious ways to make asynchronous design exceptionally efficient. For example the evemential camera provided by Prophesse can capture 10,000 images per second, having 1,000 more sensibility and a consumption divided by 10 compared to a classic camera [20][21]. In another area, scientifics have designed asynchronous “processors” to make machine learning. They have a behavior totally different from classical neural networks, they are by construction close to the biologie. They are more energy efficient and can make unsupervised learning that the classical one can’t do at all [22].

Conclusion

The mining of bitcoin or other cryptocurrency consumes a large quantity of energy, we have in objectif to reduce it in order to make our ASIC miner much more efficient thanks to the asynchronous electronic. On the other hand, we have a huge quantity of electronic devices consuming a large share of global energie. The world wide consumption in electronics can reach 20.9% in 2030 [23]. We have nowaday an issue concerning electric consumption and much research has shown many benefits of asynchronous electronics. Some niche applications have been made using asynchronous electronics having many advantages in terms of energy but also functional intrinsic to this technologie. Concerning energy consumption, asynchronous electronics may have a great future [24].

— Bibliographie —

[1] BOHR, Mark T. et YOUNG, Ian A. CMOS scaling trends and beyond. IEEE Micro, 2017, vol. 37, no 6, p. 20–29.

[2] WALDROP, M. Mitchell. More than moore. Nature, 2016, vol. 530, no 7589, p. 144–148.

[3]

https://www.usinenouvelle.com/article/la-loi-de-moore-est-morte-vive-la-loi-de-huang.N1010 424

[4]

lemondeinformatique.fr/actualites/lire-la-fin-de-la-loi-de-moore-provoquerait-une-crise-econo mique-33223.html

[5] IWAI, Hiroshi. Impact of the end of CMOS miniaturization on ICT and the world after that. In : 2018 18th International Workshop on Junction Technology (IWJT). IEEE, 2018. p. 1–5.

[6] IWAI, Hiroshi. End of the downsizing and world after that. In : 2017 Fourth International Conference on Mathematics and Computers in Sciences and in Industry (MCSI). IEEE, 2017. p. 138–143.

[7] RATNESH, R. K., GOEL, Amisha, KAUSHIK, G., et al. Advancement and challenges in MOSFET scaling. Materials Science in Semiconductor Processing, 2021, vol. 134, p. 106002.

[8] CHAUHAN, Yogesh Singh, LU, Darsen, VENUGOPALAN, Sriramkumar, et al. FinFET modeling for IC simulation and design: using the BSIM-CMG standard. Academic Press, 2015.

[9]

https://cset.georgetown.edu/article/analysts-believe-that-a-single-tsmc-5nm-wafer-costs-170 00/

[10] https://www.asicminervalue.com/miners/bitmain

[11] WILLIAMS, R. Stanley. What’s Next?[The end of Moore’s law]. Computing in Science & Engineering, 2017, vol. 19, no 2, p. 7–13.

[12] W. Keister, A. E. Ritchie, and S. H.Washburn. The Design of Switching Circuits. Van Nostrand, Princeton, New Jersey, 1951.

[13] KESSELS, Joep et MARSTON, Paul. Designing asynchronous standby circuits for a low-power pager. Proceedings of the IEEE, 1999, vol. 87, no 2, p. 257–267.

[14] PAVER, N. C., DAY, Paul, FARNSWORTH, Craig, et al. A low-power, low noise, configurable self-timed DSP. In : Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE, 1998. p. 32–42.

[15] LAW, Chong Fatt. Design methodologies for low-power asynchronous-logic digital systems. Nan. Tech. Univ, 2008.

[16] ZHOU, Liang, PARAMESWARAN, Ravi, PARSAN, Farhad A., et al. Multi-Threshold NULL Convention Logic (MTNCL): An ultra-low power asynchronous circuit design methodology. Journal of Low Power Electronics and Applications, 2015, vol. 5, no 2, p. 81–100.

[17] VAN BERKEL, Kees, BURGESS, Ronan, KESSELS, Joep, et al. Asynchronous circuits for low power: A DCC error corrector. IEEE Design & Test of Computers, 1994, vol. 11, no 2, p. 22–32.

[18] HSU, Chun-Ming, STRAAYER, Matthew Z., et PERROTT, Michael H. A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma $ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation. IEEE Journal of Solid-State Circuits, 2008, vol. 43, no 12, p. 2776–2786.

[19] KIM, Juyeon, JOO, Deokjin, et KIM, Taewhan. An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. In : Proceedings of the 50th annual design automation conference. 2013. p. 1–6.

[20] GALLEGO, Guillermo, DELBRÜCK, Tobi, ORCHARD, Garrick, et al. Event-based vision: A survey. IEEE transactions on pattern analysis and machine intelligence, 2020, vol. 44, no 1, p. 154–180.

[21] https://rpg.ifi.uzh.ch/research_dvs.html

[22] LIU, Dingbang, YU, Hao, et CHAI, Yang. Low‐power computing with neuromorphic engineering. Advanced Intelligent Systems, 2021, vol. 3, no 2, p. 2000150.

[23] JONES, Nicola. How to stop data centres from gobbling up the world’s electricity. Nature, 2018, vol. 561, no 7722, p. 163–167.

[24] LEWIS, Michael John George. Low power asynchronous digital signal processing. The University of Manchester (United Kingdom), 2000.