Event-Driven & Reactive Hardware

Past Software Makes Hardware chapters introduced a hardware abstraction ladder, including physical, structural, and behavioral layers. Here we’ll dig into the common patterns at the behavioral layer — which will look surprisingly familiar to users of modern, asynchronous, concurrent environments such as NodeJs or Python’s asyncio.

Behavioral hardware programming — or as chip-folks call it, hardware *description* — came into vogue around the mid 1980s. The industry’s two most popular hardware description languages (HDLs), Verilog and VHDL, were both introduced in these early HDL days. While Verilog and VHDL both support the lower structural layer, their new contribution was the addition of the behavioral features described here. The general idea is that instead of directly programming a piece of hardware’s *structural content* — essentially a hierarchical list of components and connections — designers can describe what a hardware block *does*, at a slightly higher level of abstraction.

Nearly every complex piece of digital hardware you use was written in either Verilog or VHDL. This includes essentially every chip required for reading this article — your computer (or smartphone) CPU, the network interface transmitting and receiving this document, and the GPU rendering it on your screen.

These languages generally resemble a C++-ish level of abstraction and productivity. But HDLs centrally integrate a few programming paradigms which look, well, awfully shiny and new to a lot of programmers in 2019…