A via is a conduit for transferring a signal from one layer to another. It seems almost too straightforward to mention, but vias are one of the key drivers of PCB producibility (note that producibility is a synonym for cost). The substrates and chips that drive electronics from the nano-sphere to the world as we can see with our own eyes make use of vias.
| What’s comprises a via?
In the simplest terms, a two-layer board has its circuit pattern etched on both sides with capture pads placed where the electrons want to go from one side to the other. At that point, a drill that is smaller than the pad goes through both leaving behind a hole with a lip of metal around it top and bottom. The hole is cleaned, de-smeared, and de-burred ahead of plating. Instead of removing copper as we do in the etch process, we add copper to the circuit pattern and the newly formed hole at the same time.
As an aside, the plate-up process is essential to the circuit pattern as well. It’s much easier to start with a thinner veneer of copper to be chemically removed in the first place and then add more. This is especially true when it comes to narrow lines and spaces.
|When all is said and done, we’re not designing the traces and polygons; we’re designing the space between them.
For this reason, the traces will have more copper than the “barrel” of the via. It seems like the most common DFM question from the fab vendor is to ask if they can reduce the minimum copper thickness in the barrel called out on the fab drawing or by association through an IPC reference document.
So, now we have two layers of copper with locations for holes that are drilled away and plated to create the connections. We’re done, right? Nope! Add another layer pair (or ten) and the natural misregistration of the circuit patterns from layer to layer start to confine the drill to a smaller target if it is to stay within all of the pads. We compensate with a larger pad on each layer or by restricting the misregistration of the individual layers.
The ratio of via pad size to drill size has a lot to do with yields in fabrication. IPC-2221 and other specs cover the via geometry. The rule of thumb for the capture-pad diameter is adding 0.25 mm to the finished hole size.
Pro tip: The tolerance for vias should be plus .08 mm (3 mils) and minus the nominal diameter so that a .20 mm via has a tolerance of +.08/-.20.
In my first anatomy lesson on solder joints, we talked about protecting the copper from the elements. The via gets a nice coating of whatever surface finish is used to cover the rest of the copper. Depending on the application, the via could also be filled, plugged, tented, or left with its shiny protective coating exposed. Let’s break those alternatives down in more detail. Note: via glossary at the bottom of this article.
Filled vias (conductive)
Most often, it’s for heat dissipation where we want to turn the via into a more solid structure. It also adds to the current capacity as it is both electrically and thermally conductive. This is an expensive process involving epoxy resin and a metal, be it copper, silver, gold, aluminum, tin, or a combination — the usual suspects held in suspension. Tatsuta is one maker that uses such via-fill paste materials.
Plugged vias (non-conductive)
The general idea with plugged vias is to fill the via with a low-viscosity solder mask or other suitable material similar to the resin used in the laminate construction. It becomes the protector of the copper, so the extra surface finish is not necessarily required in the barrel of the via. It’s a step down in price but provides little to no thermal benefit that you’d see with conductively filled vias.
Whether it’s conductive or not, the CTE mismatch between the board material and the fill material should be kept to a minimum. Since different board materials expand at different rates, there are different fills.
Tented vias (covered)
Covered vias are a rather imprecise process where we allow the solder mask to cover the via without concern for filling it. This process can create a tiny space where air is trapped inside the via. If you contain a gas and then heat it up as we do in a PCB soldering process, you can get a mini-explosion as the expanding molecules find the weakest point in the containment and … poof — defect. A workaround for this potential problem is to specify a small opening in the middle of the tent so that the mask covers the outer metal annular ring permitting, the via to breathe. The point here is to allow the via to be situated closer to the pad without having the solder migrate down the hole. The tent then becomes part of the solder dam.
Via in pad
Mechanically drilled vias are often arrayed within the large central pad of QFN and QFP device, or most any linear regulator to act as a path for thermal dissipation. For the sake of solderability, they are typically filled in one way or another.
The micro-via-in-pad process is most likely why you are here (thanks for reading down this far!). We can usually get away with offset through-hole vias until the pitch of the BGA devices gets below 0.65 mm. At the next node, 0.5 mm pitch, there is no longer enough space for a via between the pads. We have to pivot over to HDI construction using micro-vias. These u-vias are easy to fill, cap, and finally finish along with the rest of the solderable pads. Cross section shown below:
The jump from using a drill to using a laser comes with a number of conditions.
- The first is that the micro-vias have a limit to their aspect ratio. The plating has a hard time finding its way down a long and narrow well so keeping the diameter larger than the depth is advised. Preferred practice may be a ratio of 0.6 depth to 1 width so that the via is wider than it is deep.
- This has the effect of driving the market for thinner and thinner dielectric materials. These thinner materials bring the reference plane closer to the trace which reduces the characteristic impedance of the trace. We often have to create openings in the second layer and reference the third or even deeper layers in order to get a reasonably thick trace of the desired impedance.
- The laser needs a robust layer of metal on the target layer or it will burn right through. Different materials have different responses to different wavelengths of laser energy. Here is a short white paper on how lasers are used in the PCB fabrication process.
- This is the tip of the HDI iceberg. The gap between designing with normal vias and microvias is equivalent to the difference between rigid and flex; fairly substantial. I hope this has provided some insight. It’s more than a copper plated hole as you will notice while you browse the handy list below.
These aren’t the official, according-to-Hoyle canon, only my understanding in my own words. The real specs are available for purchase. This is what you get for free.
Annular ring This is what’s left over in the metalization around the via hole after all is said and done.
It’s also one of the key differences between the three reliability levels according to IPC standards. Toys are Class 1 where the ring doesn’t have to go all the way around the hole on every layer. Consumer electronics are Class 2 where tangency is the limit. Aerospace and life support are examples of Class 3 and the annular ring must be complete and oversized by 0.13mm (5 mils) all the way around.
ALIVH An acronym for Any Layer Interstitial Via Hole that is licensed by Panasonic and is common wherever you need micro-vias all the way through the board, especially smart phones.
Back drill Where you remove z-axis stubs for signal integrity of high speed connections; common in thick backplanes or whenever a through hole via is used to span a few layers that leave a substantial quantity of unconnected layers below. The back drill is larger than the original size via and remains un-plated.
Blind via A controlled depth via that starts on an outer layer and ends within the stack-up.
Break-out. This is when the drill is off center enough to escape the geometry of the pad. We can live with this in most circumstances if we add a fillet at the via-trace junctions.
Button plating A one-sided approach to via fill common with flexes and BGAs where a probe-friendly opening is desired.
Core via In a sequential lamination process, the core via is a mechanically drilled hole of the typical size that is performed on the central stack of layers prior to the rest of the lamination cycles.
The core can be two layers or a multiple of two with four, six and eight being common. Whatever the number, it will be the “N” in a 1+N+1 or 2+N+2 stack-up. Core vias are buried vias by definition but not all buried vias are core vias.
Drill Chart A key part of the fab drawing that gives the size, tolerance, plating and quantity or each type of hole in the board.
Electro-less copper This is the seed material that adheres to the raw drilled hole.
Electroplating The step following electro-less copper but still using copper for the most part. There are quite a number of other steps from the initial drill to the finished via. This is just an overview and different boards will require different steps.
Fence A term for the ground vias that are placed along the length of a controlled impedance line to isolate the sensitive circuit from the aggressively noisy circuits.
G-via Gotcha! There’s no such thing. I just can’t think of anything that starts with G other than ground via and that’s self-explanatory. If I try to use every letter of the alphabet, we’ll be here all day. You’re still here, right?
HDI High Density Interconnect is the present and future of PCB design. It boils down to the use of micro-vias and all of the attendant requirements.
Impedance Vias come in around roughly 30 ohms which is a huge discontinuity on an RF or high-speed line. RF is typically routed on top and diff-pairs are usually limited to two vias per side. We have the latitude on diff-pairs because they need to match each other so the discontinuities tend to cancel each other out. Single ended lines see massive reflections at the via.
Microvia Generally, any vias less than 0.15 mm (6 mil) hole size are considered micro-vias. It’s assumed that they are created with a laser and only span one layer at a time with the exception of a skip-via that goes through two layers.
As we stack them, the short-hand for the stack-up relates to how many layers of microvias (and subsequent lamination cycles) are used to create the board. In a 3+N+3 stack-up, the threes represent individually formed microvias from layer 1–2, 2–3 and 3–4 as well as the same stack counting up from the bottom.
It makes sense to add a layer to both sides of the core while the board is in the press so the two numbers normally match. Another wrinkle on this process was described in my favorite stackup.
Outgassing Your basic failure mode where trapped air finds equilibrium by blowing through the coating.
PTHV Plated Through Hole Via; a normal via or a larger hole to allow insertion of traditional non-SMD components.
Via-in-pad Covered in the body of this post and just what it sounds like.
Via Systems They got swallowed up by TTM. That’s what they get for swallowing up DDi. Nothing to do with this post but the consolidation in the U.S PCB industry is leaving us with fewer domestic choices while some other country seems to spawn a new fab shop too often.
WXYZ Have a nice day.