Confessions of a PCB designer — on Solder Mask
Board design is central to both the fabrication and the assembly processes and there are, occasionally, some conflicts between the two camps. Masking off the space between the solderable landing pads is one of those areas where conflicting goals come to the fore.
IPC specifications cover the requirements very well in terms of what the mask is supposed to do. The preamble to IPC-SM-840D puts it this way -
The solder mask materials described herein, when applied to the printed board substrate shall prevent and/or minimize the formation and adherence of solder balls, solder bridging, solder build-up and physical damage to the printed board substrate. The solder mask material shall help retard electromigration and other forms of detrimental or conductive growth.
The document bolds the word “shall” so that you know that they are King-James-Version serious! (deemphasis mine). Loyal followers of these notes would perhaps notice that this is the first time I’ve quoted anything verbatim. The stilted language of those two sentences sure look scholarly so I’ll be doing this from time to time instead of inserting links to entire web pages that come and go. You’ll find those at the bottom of this page for reference.
Besides the authority of the institution, there are thousands, maybe even millions of component data sheets that describe the application of masking. After reading or at least skimming a measurable percentage of those documents, I’ve concluded that most device manufacturers prefer a land pattern where the mask is designed to be larger than the metal pad. When it’s the other way around, the technique is referred to as Solder Mask Defined or SMD. That acronym makes me think of Surface Mount Device so it could be a point of confusion.
Just remember that NSMD means expansion of the mask and SMD means contraction. They’re never the same size because layer-to-layer registration doesn’t work that way. If you tape out the board with the metal and mask being equal, you should also provide a note regarding what to do in terms of the fabricators global micro-editing of the mask layers. Or, you could leave it to chance.
“Never cross the streams”
Just like our heroes from the Ghostbusters were cautioned to never cross the plasma streams, we are admonished to never mix SMD pads with the preferred Non-Solder-Mask-Defined (NSMD) pads. Never say never. The data sheet for Intel’s Skylake processor calls for both types with the SMD pads for the central grid of power balls and “normal” NSMD pads for the fine-pitch signals that are mapped out around the core.
The reason behind this split decision is that they intend for us to flood over the power and ground pins. If you have a metal pad inside a larger mask opening and then pour copper over the entire pad, it would effectively grow to the size of the mask. The normal amount of solder paste may not be sufficient for that much of a pad. The collapse of the BGA during reflow may not be even without compensation of one or more of the parameters. Metal, mask and paste go hand-in-hand in the formation of a good solder joint. When it comes down to the smaller pads on the edges, the NSMD is preferred. One reason from Intel itself follows -
Vision registration on copper fiducials (reference points) will give exact location of the site. With SMD pads, the misrepresentation error of the solder mask will also shift the location of the entire site relative to vision fiducials.
What they’re saying is that the screened on LPI mask doesn’t align with the circuit pattern well enough for accurate placement of fine-pitch components. Growing the mask out of the way of the metal plating is the default.
A little history here:
Let’s go back to when 28 nanometers meant something. Of the four major mobile-processor vendors, Intel was the hold-out in sticking to the notion that the motherboard — or Main Logic Board — had to have a non-HDI solution. Their circa 2013 Baytrail family featured reference designs using what they called “via channel” technology where you could fan-out the device using only through-hole vias rather than the micro-vias embraced by Nvidia’s Tegra, Quacomm’s Snapdragon and Samsung’s Exynos families. That hesitation left them with big, power-hungry chips that eventually cost them their number one spot in the world-wide market — at least in my opinion. Of course, there are other factors. They’re on board (pun intended) and working hard to regain momentum.
We like NSMD technology for another reason. Again, from Intel’s app notes on BGA packaging -
One disadvanatage (sic) of SMD pads is that the fatigue life has shown to be lower then (sic) NSMD pads through long term reliaiblity (sic) testing. Because of this issue, the solder mask angle at the pad edge has been thinned on many new package designs to minimize the mask impingment (sic) on the solder ball.
Damn it, Intel, proof-read your publications! I think they’re trying to say something about the stressed area at the base of the solder joint where the mask overlaps the pad on solder mask defined lands. The cross section resembles a microscopic mushroom where a crack forms between the stem and the cap of the mushroom. Latent defects are the worst because it’s your customer that finds them when the gizmo quits doing its thing and ends up in the pile.
It’s not all bad for SMD though. The mask acts as a tie-down around the pad to keep it from lifting. The fab shop is totally down with that because they usually get the blame from the assembly house when the pad peels off the board. Slick dielectric materials like Teflon and of course, flex circuits are notorious for delaminating. A well-cured solder mask provides some necessary adhesion.
Pro tip:
Individually matching the mask to the pad size is a good compromise if you have to flood over some pads while others get connected with a trace. The effective size is matched but you still have the thermal response of the disparate geometries.
Below a certain pin-pitch threshold, we will be forced to use solder mask defined lands. At 0.35 mm pitch, the minimum dam of 100 microns will only leave us 250 to work with. Now, we’d still have to account for mask expansion so our plated pad is shrinking down to somewhere around 200 to 150 microns depending on the type of mask technology. That’s pretty small for a micro-via-in-pad solution. Recall that the tiny pad needs all the help it can get to remain attached to the board. For this size micro-BGA, I would go with a 270 micron pad (which leaves > three-mil air gap pad-to-pad) and cover the edges of the pad with a 200 micron mask opening. Your resulting solder mask dam is 150 microns.
The data sheet on this part is likely to be vague on the solder mask application and they will probably advise you to contact your fabrication vendor to figure this out. That seems like a cop-out but they’re right. It’s pretty-much a given that we’ll need to use a Laser Direct Imaging (LDI) rather than an Liquid Photo Imageable (LPI) mask. These chip-scale parts and the 01005 caps that feed them are off the charts of the IPC specs. We’re on our own so, I’m sharing some baseline numbers in case you find yourself designing these into your next generation products.
Maxim provides a concurring opinion to expand the mask rather than to contract it:
Although both NSMD and SMD pads are used in applications, NSMD pads are recommended. NSMD pads have the advantages of more precise pad dimension and better solder joint reliability at board side. Only one type of a pad (NSMD or SMD) and one type of pad surface finish should be used at a given footprint.
…and they also provided this useful side-by-side diagram of the two types of pad-stack.
Symmetry leads to better results and this is especially true of the smaller discrete components. RF engineers like to have low-inductance current loops and we get that by flooding over the ground pins while it’s just a trace on the signal/power side of the little caps. Although the finished board performs very well, this is a disaster waiting to happen on the assembly line.
The rate at which each solder joint enters the reflow state should be kept as similar as possible. If the solder of both leads of the part do not solidify at the same moment, the one that freezes first will want to pull the component away from the other one. It’s a common defect known as a tombstone for its resemblance to the graveyard monuments. Ironically, this same capillary action is what helps the larger parts center themselves over the pads as long as the temperature profiles in each nano-climate is reasonably close.
More free stuff down here!
Intel BGA packaging
Flex Circuit Cheat Sheet
Maxim WLSP design guideline
More Notes on solder mask
