MCU Designer’s Intro to FPGA Hardware
If you look at the people designing embedded systems or “things” for the Internet of Things (IoT), there are about five or six software developers for each hardware design engineer.
Furthermore, in the case of the hardware design engineers, the vast majority use microcontrollers (MCUs) as their processing engine of choice. Relatively few, in the scheme of things, include FPGAs in their “bag of tricks.” This is unfortunate, because FPGAs can offer a lot of performance advantages for the right sort of problems (see also Using FPGAs to Accelerate C/C++).
One of the issues is that a lot of folks on the MCU side of the fence don’t really understand what FPGAs are or what they do. I think it’s fair to say that, if questioned, most of them would say something like, “An FPGA is a component whose function(s) can be defined,” but that’s about as far as they would care to go.
This is a shame, because FPGAs are really rather clever. Let’s consider a generic representation of what would be considered to be a mid-range device at the time of this writing (note that the general-purpose input/output (GPIO) banks can be individually configured to support a variety of interface standards).
If we use the programmable fabric (the green logic blocks in the “Bird’s-eye view” part of the diagram) to implement a function like a counter, that function is said to be “soft.” However, the FPGA may also include “hard” functions implemented directly in the silicon, such as digital signal processing (DSP) blocks containing configurable multipliers, SRAM blocks, and so forth.
A low-end FPGA might contain only a few GPIO banks and a few tens of thousands of logic blocks, while a high-end device may contain hundreds of thousands of logic blocks, megabits of memory, thousands of DSP blocks, one or more hard processor cores (a Zynq UltraScale+ SoC FPGA from Xilinx contains a quad-core 64-bit Arm Cortex-53 and a dual-core 32-bit Arm Cortex-R5, for example), multiple hard interface blocks (I2C, SPI, USB, UART, CAN, etc.), a thousand-plus GPIOs, and so forth.
However, the focus of this column is the programmable fabric, which is presented in the form of the green logic blocks in the above illustration. This is what really differentiates FPGAs from other device architectures.
This programmable fabric can be visualized as comprising “islands” of programmable logic in a “sea” of programmable interconnect. The programmable logic blocks contain things like look-up tables (LUTs), multiplexers, and registers.
A 4-input LUT can be used to represent any 4-input logical function, and LUTs may have anything from 4- to 8-inputs depending on the FPGA. Meanwhile, the programmable interconnect can be used to connect the outputs from any logic blocks to the inputs of other logic blocks.
Even if the FPGA contains nothing but programmable fabric and SRAM blocks, it can be used to create soft functions as complex as MCUs, and you can have multiple instantiations of these functions if you wish. If the FPGA also contains things like DSP blocks, then the programmable fabric can be used to connect these blocks and process the data going in and out of them. And if the FPGA contains hard processor cores, the programmable fabric can be used to create hardware accelerators to speed the execution of bottleneck code.
In my next column we’ll look at the FPGA design flow. In the meantime, I welcome any comments and questions.
