PmFPGA journeyAs mentioned in a previous post one of the things triggered by my descent into the nand2tetris hole was the decision start working with…Jul 3
Nanda SiddhardhaDSP for FPGA: Simple FIR Filter in VerilogThe main focus of this project is on the implementation of a FIR in HDL (Verilog specifically, but the concept can be easily translated to…Mar 10
Marek PikułaRISC-V Summit Europe 2024 SummaryThis week, I had the pleasure of attending the second edition of RISC-V Summit Europe in Munich, Germany, on behalf of Samsung R&D.Jun 29Jun 29
Umer FarooqA PYNQ-Z2 Guide for Absolute Dummies — Part I: Fun with LEDs and SwitchesIf you just purchase the PYNQ-Z2 board, and looking at the official documentation seems overwhelming, then this is the best tutorial for…Sep 6, 20205Sep 6, 20205
Cole JVUnderstanding Hard Core vs. Soft Core Processors: A Friendly GuideHey there! Let’s dive into the world of processors, specifically hard core and soft core processors. If you’ve found the information online…Jun 26Jun 26
PmFPGA journeyAs mentioned in a previous post one of the things triggered by my descent into the nand2tetris hole was the decision start working with…Jul 3
Nanda SiddhardhaDSP for FPGA: Simple FIR Filter in VerilogThe main focus of this project is on the implementation of a FIR in HDL (Verilog specifically, but the concept can be easily translated to…Mar 10
Marek PikułaRISC-V Summit Europe 2024 SummaryThis week, I had the pleasure of attending the second edition of RISC-V Summit Europe in Munich, Germany, on behalf of Samsung R&D.Jun 29
Umer FarooqA PYNQ-Z2 Guide for Absolute Dummies — Part I: Fun with LEDs and SwitchesIf you just purchase the PYNQ-Z2 board, and looking at the official documentation seems overwhelming, then this is the best tutorial for…Sep 6, 20205
Cole JVUnderstanding Hard Core vs. Soft Core Processors: A Friendly GuideHey there! Let’s dive into the world of processors, specifically hard core and soft core processors. If you’ve found the information online…Jun 26
David SuchThe FPGA Programming Handbook — A ReviewPackt are the publishers of The FPGA Programming Handbook by Frank Bruno and Guy Eschemann. Recently, they were kind enough to provide me…May 20
Shadeeb HossainProgramming an FPGA Board to check ‘AND’ Digital Logic Gate operationHi Everyone,Jun 24
Wei-Yuan,Weng ( Victor)Static Timing Analysis _(2) _Derive the formula for timing constraintRegarding STA, the follow-up description will be added, the STA description of the classic timing. The following figure shows the classic…Apr 2, 2022
