Ayush Dixit 💾💽Vitis Hls SigSegv ErrorWhile working with simulation for deep neural networks generally have to deal with large array sizes eg 1080*1920 and so on ,Performing…Nov 7
Muhammed KocaoğluGaussian Filter Using Vitis HLSIn my previous post, I implemented the Gaussian filter by using VHDL with 2 different methods. In the first method, I used floating-point…Dec 18, 2021
InThoughtworks: e4r™ Tech BlogsbyManikantaHigh Level Synthesis for Accelerator DesignToday, the demand for accelerated computing and hardware accelerators is continually rising. However, developing hardware accelerators…Jan 19Jan 19
Inlogic-synthesis-in-vlsibyHarshada BelgiHigh Level Synthesis in VLSIWith the advancements in the digital electronic technologies and devices that are integrating System-on-chip (SoCs), the design complexity…Mar 19, 2021Mar 19, 2021
InThoughtworks: e4r™ Tech BlogsbyNimalanAccelerating an Lorenz ODE Solver with DahliaIn this article, we will design a Lorenz ODE Solver in Dahlia, exploring the use of Dahlia records, functions, and single-precision floats…Jan 10Jan 10
Ayush Dixit 💾💽Vitis Hls SigSegv ErrorWhile working with simulation for deep neural networks generally have to deal with large array sizes eg 1080*1920 and so on ,Performing…Nov 7
Muhammed KocaoğluGaussian Filter Using Vitis HLSIn my previous post, I implemented the Gaussian filter by using VHDL with 2 different methods. In the first method, I used floating-point…Dec 18, 2021
InThoughtworks: e4r™ Tech BlogsbyManikantaHigh Level Synthesis for Accelerator DesignToday, the demand for accelerated computing and hardware accelerators is continually rising. However, developing hardware accelerators…Jan 19
Inlogic-synthesis-in-vlsibyHarshada BelgiHigh Level Synthesis in VLSIWith the advancements in the digital electronic technologies and devices that are integrating System-on-chip (SoCs), the design complexity…Mar 19, 2021
InThoughtworks: e4r™ Tech BlogsbyNimalanAccelerating an Lorenz ODE Solver with DahliaIn this article, we will design a Lorenz ODE Solver in Dahlia, exploring the use of Dahlia records, functions, and single-precision floats…Jan 10
Inlogic-synthesis-in-vlsibyHarshada BelgiHigh Level Synthesis using Linear RegressionHigh Level Synthesis (HLS) works at the algorithmic level in hardware design systems. HLS tools provide automatic conversion from…Apr 30, 2021
InThoughtworks: e4r™ Tech BlogsbyNimalanDahlia Part 1: Affine types for High Level SynthesisIn this article we will be looking at the affine type system and it’s application in FPGA based accelerator design using Dahlia.Dec 28, 2023
Eymen UnayThe Race To Abstract VerilogThough its simplicity to realize a project, Verilog (or any other HDL) is not easy to reuse and scale. The lack of object oriented view of…Sep 13, 2022
