Hao-Wei ChanDeepGate: Unlocking the Power of Logic Circuits with Graph Neural NetworksWe breakdown DeepGate’s innovative use of GNN in IC design modeling and analysisJun 30
EDA AcademyAdvanced Timing Signoff Techniques for Integrated Circuit Designadvanced timing signoff methodologies, detailed case studies, and the latest cutting-edge technologies in digital design.Jun 129Jun 129
EDA AcademyPower Analysis Techniques for High-Efficiency IC Designadvanced methodologies in power analysis, presenting detailed case studies and the latest cutting-edge technologies in digital design…Jun 126Jun 126
Hao-Wei ChanDeepGate: Unlocking the Power of Logic Circuits with Graph Neural NetworksWe breakdown DeepGate’s innovative use of GNN in IC design modeling and analysisJun 30
EDA AcademyAdvanced Timing Signoff Techniques for Integrated Circuit Designadvanced timing signoff methodologies, detailed case studies, and the latest cutting-edge technologies in digital design.Jun 129
EDA AcademyPower Analysis Techniques for High-Efficiency IC Designadvanced methodologies in power analysis, presenting detailed case studies and the latest cutting-edge technologies in digital design…Jun 126
Tsungyu Liu[Intro] — 7 Using Multiple Modules in VerilogLet’s review Full Adder again. Below is the truth table of Full AdderSep 18
EDA AcademyMastering Design Rule Checking (DRC) for High-Quality IC Designadvanced DRC methodologies, specific case studies, and the latest cutting-edge technologies in digital design…Jun 126
Louie Wu[Chatgpt] 數位IC設計師如何用chatgpt寫出一個讀入verilog .v檔,並印出module上所有I/O的signal name的python程式前言:Feb 1, 2023