Kushagra AgrawalVLSI: Physical Design (PD P4) — Sanity checks in PDClean the input first, then expect a clean outputMar 71
Radha KulkarniWhat is the role of floorplanning in VLSI design?Floorplanning plays a crucial role in VLSI design by determining the physical placement of functional blocks on the silicon die. It serves…Jul 28Jul 28
AgnathavasiICC2 —Usefull commands1. Get the count of Clock buffers? report_device_group -detailed clock_networkNov 20, 2023Nov 20, 2023
VLSIPDPhysical Design in VLSI: Why It Matters, What It Entails, and How It’s DoneIn the realm of Very Large Scale Integration (VLSI), physical design is a critical phase that bridges the gap between a circuit’s logical…May 20May 20
Kushagra AgrawalVLSI: Physical Design (PD P4) — Sanity checks in PDClean the input first, then expect a clean outputMar 71
Radha KulkarniWhat is the role of floorplanning in VLSI design?Floorplanning plays a crucial role in VLSI design by determining the physical placement of functional blocks on the silicon die. It serves…Jul 28
AgnathavasiICC2 —Usefull commands1. Get the count of Clock buffers? report_device_group -detailed clock_networkNov 20, 2023
VLSIPDPhysical Design in VLSI: Why It Matters, What It Entails, and How It’s DoneIn the realm of Very Large Scale Integration (VLSI), physical design is a critical phase that bridges the gap between a circuit’s logical…May 20
Kushagra AgrawalVLSI: Physical Design (PD P5) — Ideal Clock vs Real ClockAll about Latency, Skew, Jitter, and UncertaintyMar 101
Kushagra AgrawalVLSI: Physical Design (PD P3.2) — Physical Cells in PDWe will discuss remanining Physical Cells.Mar 31
