Erik EngheiminITNEXT·2 days agoRISC-V Instruction-Set CheatsheetOverview of the RV32I base instruction-set of RISC-V processors — A number of people have tried to make sheets giving an overview of the RISC-V instruction-set, so here is my variant. I have tried to find a balance between being useful and easy to read. That means some things I have excluded from this overview. For instance, most instructions dealing…Risc V4 min read
Maksim Lin·6 days agoFlutter 3: The year of the Desktop!and some RISC-y business… — Flutter 3 !!! Flutter 3 is out today! And for me, the big news item is stable support for Linux Desktop 🎉🎉 (and also MacOS). …Flutter3 min read
ztex, Tony, Liu·May 11Design Review — Backtrace in RISC-VIntroduction Today, we’re going to cover my experience about conducting backtrace under FreeRTOS + RISCV, with interference brought from compiler option. After we get the stack and dump it. Now here are what developers already know: Registers value The address of the instruction cause the problem (this leads to which exactly…Freertos8 min read
Erik EngheiminITNEXT·May 4RISC vs CISC Microprocessor Philosophy in 2022A new look at the RISC vs CISC debate by framing it as a debate on how to spend a limited transistor budget to achieve performance. — PEOPLE LIKE to think about the distinction between RISC and CISC processors as being about some specific set of features or some magical limit on number of instructions or transistors. Few Instructions Doesn’t Mean RISC Let us get some very obvious misconceptions out of the way. Because RISC stands for Reduced Instruction Set Computer, there…Risc15 min read
Erik EngheiminITNEXT·Apr 13Advantages of RISC-V vector processing over x86 style SIMDInstead of adding SIMD instructions such as MMX, SSE, AVX or Neon, RISC-V designers are focusing on vector processing. — A well known way of processing multiple streams of data in parallel is through the use of SIMD instructions. All major chip makers started adding SIMD instructions to their processors in the late 1990s. MMX was added to Intel’s Pentium processor in 1997. …Risc V18 min read
ztex, Tony, Liu·Apr 12RISC-V trap (exception) handlerIntroduction Does this bother you? You are an embedded system engineer, you just deploy a build onto your machine. However it crash unprompted … you have not clue but the guess. (Well, of curse you can always use JTAG, I guess I’ll write another article about this later) It would be…Freertos5 min read
Exergy Connect·Apr 7Decentralized needle-finders 🧲 — Improving software security 🔒 and network reliability through architectural Proof-of-Test ✓New RISC-V architectural primitives in support of PoT rewards — The Bitcoin industry is booming; though estimates vary, sources put the global energy usage invested in mining activities around 100 TWh per year — more than my home country of The Netherlands. …Risc V3 min read
Erik Engheim·Apr 3Demystifying RISC Microprocessor PhilosophyDeep misconceptions between RISC and CISC processor still remain. Let us try to clarify. — I write a lot about microprocessors where I talk briefly about RISC and CISC processors. …Risc V11 min read
Erik EngheiminITNEXT·Mar 26Vector Processing on CPUs and GPUs ComparedSIMD, CUDA, SSE, MMX, SVE2 and RVV how different are these approaches to parallel processing? — Modern CPUs and GPUs can all process a lot of data in parallel so what exactly makes them different? …Gpu Computing27 min read
Erik EngheiminCodeX·Mar 20Addressing Criticism of RISC-V MicroprocessorsIs RISC-V just a rehash of 1980s RISC ideas? Requires too many instructions to do simple stuff? — RISC-V is an instruction-set architecture (ISA) for microprocessors which people seem to either love or hate. In particular there seem to bit of rivalry between the ARM and RISC-V camp developing. It is perhaps not without reason. RISC-V and ARM represent quite radically different philosophies about how a RISC chip…Risc V16 min read
