Prachi ManglikManaging AXI Transactions with Separate Read and Write Agents in UVM: A Detailed Solution“Optimizing UVM Testbench for AXI Address Generators: 3 Approaches to Managing Read and Write Agents”Nov 21
Muhammed KocaoğluPYUVM RAL(Register abstraction layer)Recently, pyuvm contributors added the UVM Register Abstraction Layer to pyuvm. So, I wanted to give it a try for fun. It is really good to…May 19
Prachi ManglikUnderstanding Configuration Objects and Sequence Items in UVM: A Comprehensive GuideIn UVM (Universal Verification Methodology), configuration objects and sequence items are two critical constructs that help in creating…Oct 3Oct 3
Shivam katiyarHow to integrate RAL in TestbenchThis topic holds immense popularity across various testbenches when verifying any design. I will guide you through a systematic…Jan 23Jan 23
Shivam katiyarConfigDB: The Heart of UVMThis article is for engineers who are new to verification methodologies or are in the process of adopting UVM, this focuses on the UVM…Oct 30, 2023Oct 30, 2023
Prachi ManglikManaging AXI Transactions with Separate Read and Write Agents in UVM: A Detailed Solution“Optimizing UVM Testbench for AXI Address Generators: 3 Approaches to Managing Read and Write Agents”Nov 21
Muhammed KocaoğluPYUVM RAL(Register abstraction layer)Recently, pyuvm contributors added the UVM Register Abstraction Layer to pyuvm. So, I wanted to give it a try for fun. It is really good to…May 19
Prachi ManglikUnderstanding Configuration Objects and Sequence Items in UVM: A Comprehensive GuideIn UVM (Universal Verification Methodology), configuration objects and sequence items are two critical constructs that help in creating…Oct 3
Shivam katiyarHow to integrate RAL in TestbenchThis topic holds immense popularity across various testbenches when verifying any design. I will guide you through a systematic…Jan 23
Shivam katiyarConfigDB: The Heart of UVMThis article is for engineers who are new to verification methodologies or are in the process of adopting UVM, this focuses on the UVM…Oct 30, 2023
Prachi ManglikDetailed Comparison: PyUVM vs UVM in Hardware VerificationIn the digital design, verification plays a pivotal role in ensuring the functionality and reliability of hardware before fabrication. UVM…Nov 18
Shivam katiyarUnraveling the Magic: How UVM Factory Transforms Testbench DesignThe UVM testbench is great for reusing code, but when you want to reuse it for different things, like changing how data is sent and…Oct 13, 2023
Shivam katiyarImportance of virtual sequence and sequencerTests that need to generate stimulus in a coordinated manner using multiple drivers must use virtual sequences.Oct 7, 2023
