AgnathavasiICC2 —Usefull commands1. Get the count of Clock buffers? report_device_group -detailed clock_networkNov 20, 2023
VLSIPDPhysical Design in VLSI: Why It Matters, What It Entails, and How It’s DoneIn the realm of Very Large Scale Integration (VLSI), physical design is a critical phase that bridges the gap between a circuit’s logical…May 20May 20
Srinivas Rahul SapireddyExploring Logic Synthesis with Yosys: A Tutorial OverviewIn the evolving world of VLSI design, the journey from RTL (Register-Transfer Level) to GDS (Graphic Data System) is both intricate and…Aug 11Aug 11
AgnathavasiWhy do we consider CPPR in SI timing analysis?CPPR is the common path pessimism reduction and needs to be considered wherever appropriate to remove the unwanted pessimism you are adding…Feb 15Feb 15
AgnathavasiICC2 —Usefull commands1. Get the count of Clock buffers? report_device_group -detailed clock_networkNov 20, 2023
VLSIPDPhysical Design in VLSI: Why It Matters, What It Entails, and How It’s DoneIn the realm of Very Large Scale Integration (VLSI), physical design is a critical phase that bridges the gap between a circuit’s logical…May 20
Srinivas Rahul SapireddyExploring Logic Synthesis with Yosys: A Tutorial OverviewIn the evolving world of VLSI design, the journey from RTL (Register-Transfer Level) to GDS (Graphic Data System) is both intricate and…Aug 11
AgnathavasiWhy do we consider CPPR in SI timing analysis?CPPR is the common path pessimism reduction and needs to be considered wherever appropriate to remove the unwanted pessimism you are adding…Feb 15
gowsikaDharmarajStatic Timing Analysis: A deeper diveAuthor’s kind note: I’m writing this article to make the readers understand and appreciate the art of timing in the digital circuits.Jan 1
Srinivas Rahul SapireddyUnderstanding Delay Calculation and Static Timing Analysis Using OpenSTA: A Comprehensive TutorialIntroductionSep 8
