Digital Systems — Intro to VHDL
The language of the science
When working on hardware systems the modern solution to solving circuit designs and determining boolean algebra solutions is using something called VHDL. VHDL is a digital hardware language designed for circuit inputs and outputs. The value of VHDL is that it is field applicable. This means that all you need to change is the VHDL code on any FPGA, which is a field programmable array. This allows you to make changes without having to change the hardware.
An example of an FPGA is the BASys3 board. This is the physical hardware that the code can be downloaded too. The file type of VHDL is a .bit, not an executable or a .exe, file. The program Vivado has a free version that you can download here. Vivado is software that is used to implement VHDL. It also has a professional version that you can purchase. Something to keep in mind is that it is a large file to download.
Boolean Algebra
The basis for VHDL, determined by the committee that designed VHDL, is through Boolean Algebra, BA. BA is a way that digital programs can help determine if something should output a zero or one. The one and zero can be determined as having voltage or not having voltage.
BA uses truth tables to determine the BA equations and circuit diagrams. The BA equations are created using logic gates which you can learn more about here. A truth table is when you are given an input, it provides an easier way to see the result, output, of a group of different logic gates. In VHDL, BA equations is done by:
Example 1:
f <= X AND Y;
Reasoning:
f is the given output in VHDL. X and Y are anded together using a AND gate. In VHDL, the gate is capitalized and is considered keywords.
Example 2:
g <= (X OR Y) XOR (X AND Y);
Reasoning:
g is the output. X and Y are the inputs. In VHDL, the compiler cannot determine one gate pretense over another. Therefore, parenthesis must be used to determine what gate is done before another. In the above example, the OR and AND gates are done before the XOR gate.
Basic VHDL Program
The following is a basic MUX program. A mux is a type of commonly used process in logic design. I will cover this in a future article. ieee.std_logic_1164 is the standard library for all VHDL and is present in Vivado for each program.
LIBRARY IEEE;
use ieee.std_logic_1164:all;
ENTITY mux IS
PORT( a,b,c: IN std_logic;
g: OUT std_logic;)
end entity;
ARCHITECTURE behavior OF mux IS
begin
g <= (NOT(s) AND a) OR (s AND b);
end behavior;
Citations:
Thomason, Micheal. Professor. University of Tennessee. Knoxville, Tennessee. 2021
