Logic Design — Using a Full Adder and MUX in VHDL

In logic design, a major part of fully utilizing an FPGA, or a field programable array, is the full adder. For a full adder, there are three inputs: A, B, and C. The outputs are Cin, and S. The full adder is two XOR gates, two AND gates, and one OR gate. The result is explained below.

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Full Adder:

For a full adder, the result is the sum and a carryout. The carryout and sum are directed as bit values of zeroes and ones. For example, an input of 101 will have an output of Sum being 0 and carry out of 1. For the sum output, you take an XOR to the first two inputs and then XOR the last input with the resultant of the previous XOR. For the carry out you take the inputs and OR the AND gates.

VHDL Example

In VHDL, the langauge is best used in Vivado. Vivado is a software program that relies heavily on the user. You can download Vivado here. Keep in mind it is a very large program that will take up a large part of your computer. It is run by a company called Xilinx.

Logisim — Full Adder

MUX:

For a MUX or multiplexer, the results are from three inputs one of which is inverted(network). The S input gets ANDed with both of the inputs and then is sent through an OR gate.

Let's take the 101 input example through a MUX. The result value is a 0 because the S input is inverted by the NOT gate.

Logism MUX

Citations:

Thomason, Micheal. Professor. University of Tennessee. Knoxville, Tennessee. 2021

Editor. (2019, September 20). Multiplexer (MUX). Network Encyclopedia. Retrieved June 23, 2022, from https://networkencyclopedia.com/multiplexer-mux/

Vivado Download:

https://www.xilinx.com/developer/products/vivado.html