We are embarking a new series about loading and operating AI models on below bare metal stuff, not microcontrollers or SoCs but directly on hardware description languages, to be later burned and executed on an FPGA.
We will not scurry or be too slow but progress at a moderate pace. We will fundamentally understand the essential parts, digress for a little fun, move forward and in the end we will transform the model into an HDL.
We are going to lay the foundation of our journey in this part. Choosing the test AI model, architecture, hardware, hardware description language, approach, is absolutely necessary.
The Model
A very simple neural network. 1 × 1 input, 1 × 2 input coupler, 2 × 2 trainable weight matrix, 2 × 1 output coupler, 1 × 1 output, that’s it. Something like this.
Architecture
Ultimately a matrix multiplier with a high level interface through a general-purpose computer.
Hardware
Good ol’ Xilinx Spartan-6 xc6slx9.
Hardware Description Language
Verilog.
Approach
The most used arithmetic operation in processing any AI model is multiplication. In part 1 of this series we will implement an 8-bit unsigned number multiplier. In part 2 we will go to 16-bit, 32-bit and 64-bit unsigned multiplication. In part 3 we will achieve signed multiplication and start a little on floating point calculations. In the 4th part we will fully implement a floating point calculator. And in subsequent parts we will implement a basic matrix multiplier and then generic matrix multiplier. More will be cleared when we move forward. Its a long journey.
That is it for now. Part 1 coming soon.
