CCS Note 10: Lesson 5. COMP & DAC Setting And Application
Instruction
How to set up the comparator module and DAC module basic applications using CCS.
Instruction
How to utilize CCS for configuring ADC and its basic applications
Environment
This document utilizes the following setup:
Operating System: Windows x64
Code Composer Studio Version: 11.2.0.00007
Development Board: LAUNCHXL-F28379D (STM320F28379D)
Tutorial List
Reference Materials
Register Data, System, and Module Details
TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual (Rev. I) (ti.com)
Pin Mapping
Module Memory & Flash Architecture
The TMS320F2837xD Architecture: Achieving a New Level of High Performance (ti.com)
Memory Allocation Setting
TMS320C28x Assembly Language Tools v22.6.0.LTS User’s Guide (Rev. Y) (ti.com)
Some Magic Bugs Records
TMS320F2837xD Dual-Core Real-Time MCUs Silicon Errata (Rev. M)
Import Example from C2000Ware
Example 1: CPU1 — buffdac_enable_cpu01.c (CPU1 means single core.)
Project Path: C:\ti\c2000\C2000Ware_4_01_00_00\device_support\f2837xd\examples\cpu1\buffdac_enable
Example 2: CPU1 —cmpss_asynch_cpu01.c (CPU1 means single core.)
Project Path: C:\ti\c2000\C2000Ware_4_01_00_00\device_support\f2837xd\examples\cpu1\cmpss_asynch
Section 1. Basics Exercise
Connect a signal generator to produce a 60Hz sine wave with an amplitude of 0–3V.
Utilize CMPIN1P from CMPSS1 as the signal input pin, and use the Module Internal DAC to output 1.5V, which internally connects to the V- of CMPSS1 as the comparison threshold. Enable the output of CMPSS1 and observe its waveform output to GPIO14 through X-BAR.
Section 1.1 Buffered Digital-to-Analog Converter (DAC) Module
A. Introduction
B. How to calculate DACOUT(V) value:
Using DACVALA control output value.
DACREF Value: (Select one)
VDAC (Cannot be used in LaunchPad)
VREFHIA
From the user’s guide (for LaunchPad)
VREFHIx = 3V
VREFLOx =0V
C. DAC Setup
buffdac_enable_cpu01.c
buffdac_enable_cpu01.c
buffdac_enable_cpu01.c
Section 1.2 Comparator Subsystem (CMPSS) Module
A. Introduction
Neg. Input: CMPSS Internal DAC Module
Output X-BAR
CTRIPH to ePWM X-BAR
CTRIPOUTH to GPIO X-BAR
B. CMPSS Setup
cmpss_asynch_cpu01.c
cmpss_asynch_cpu01.c
cmpss_asynch_cpu01.c
X-BAR Output Pin Setting
CMPSS Module Setting
Section 1.3 Experiment Code
[Hidden] Do it yourself!!
[Hidden] Do it yourself!!
[Hidden] Do it yourself!!
Section 1.4 Experimental Results
A. CH1 (Yellow): V+ input sine wave, CH2 (Blue): V- Internal DAC output.
B. CH1 (Yellow): V+ input sine wave, CH2 (Blue): Comparator output.
Section 2. Advanced Exercise
Continuing from the example settings and configurations.
Configure ePWM1 to operate in complementary mode, generating a PWM signal with a switching frequency of 20kHz and a dead time of 1us, and enable interrupts.
Set CMPSS1 to trigger a GPIO interrupt upon an external event. When a GPIO interrupt occurs, set the Duty cycle of ePWM1A to 10%.
Hint: CMPSS1 => Output X-BAR => GPIO PIN => Input X-BAR => GPIO Interrupt
Before the next GPIO interrupt, linearly increase the Duty cycle of ePWM1A to 90% (increase it once per ePWM1A interrupt). Conversely, ePWM1B should decrease from 90% to 10%.
The schematic diagram is shown in the figure below.
Section 2.1 Experiment Code
[Hidden] Do it yourself!!
[Hidden] Do it yourself!!
[Hidden] Do it yourself!!
Section 2.2 Experiment Results
The CMPSS1 OUT can be observed to start with a very small Duty cycle for ePWM1A. As we move along the time axis, the Duty cycle gradually increases until the CMPSS1 OUT rises again and is reset. The waveform might appear a bit distorted due to the insufficient memory depth of the oscilloscope used in the demonstration.
CH1 (yellow) corresponds to ePWM1A PWM, and CH2 (blue) corresponds to CMPSS1 OUT.
