ASSIGNMENTS IN VERILOG

There are two types of assignments in veriolg

1. procedural Assignment
2. Continuous Assignment

Procedural Assignment

A procedural assignment updates the value of register data types.

Syntax:

[ delay ] register_name = [ delay ] expression;     // blocking
[ delay ] register_name <= [ delay ] expression;    // non-blocking

Description:

Procedural assignments are used for updating register data types and memory data types.

The expression in a blocking procedural assignment is evaluated and assigned when the statement is encountered. In a begin-end sequential statement group, execution of the next statement is blocked until the assignment is complete.

In a non-blocking procedural assignment, the expression is evaluated when the statement is encountered, and assignment is postponed until the end of the time-step. In a begin-endsequential statement group, execution of the next statement is not blocked and may be evaluated before the assignment is complete. A group of statements with a non-blocking assignment has similar functionality as a group of statements within a fork-join block.

The left-hand side of a procedural assignment should be one of the following:

• Register data type: reg, integer, time, real or realtime.
• Bit-select of reg, integer or time.
• Part-select of reg, integer or time.
• Memory word.
• Concatenation of any of the above.

When the right-hand side evaluates to a fewer bits than the left-hand side, the assignment to a reg does not sign-extend.

The evaluation of the assignment is delayed by the delay when the delay is specified before the register name. When the delay is specified before the expression, the expression is evaluated when the statement is encountered, and assigned in the time-step specified by the delay.

Example:

begin
  a = 0;
  #10 a = 1;
  #5 a = 2;
end             // time 0: a=0; time 10: a=1; time 15 (#10+#5): a=2;
begin
  a <= 0;
  #10 a <= 1;
  #5 a <= 2;
end            // time 0: a=0; time 5: a=2; time 10: a=1;
begin
  a <= b;
  b <= a;
end            // both assignments are evaluated before a or b changes

Continuous Assignment

A continuous assignment drives a value into a net.

Syntax:

net_data_type [ strength ] [ delay ] [ size ] net_name = expression;     // implicit
assign [ strength ] [ #( delay ) ] net_name = expression;                // explicit

Description:

Continuous assignments model combinational logic. Each time the expression changes on the right-hand side, the right-hand side is re-evaluated, and the result is assigned to the net on the left-hand side.

The implicit continuous assignment combines the net declaration (see Net data type) and continuous assignment into one statement. The explicit assignment require two statements: one to declare the net (see Net data type), and one to continuously assign a value to it.

Continuous assignments are not the same as procedural continuous assignments. Continuous assignments are declared outside of procedural blocks. They automatically become active at time zero, and are evaluated concurrently with procedural blocks, module instances, and primitive instances.

Example:

wire Out;
assign Out = A & B;
assign {COut, Sum} = A + B + CIn;
wire #50 Out = A & B;