Instantiation And Port Declaration

Instantiation

An instantiation defines a sub-component of a module.

Syntax:

module_name [ strength ] [ #( token_expression ) ] instance_name [ instance_range ] ( port_connection );
token_expression = delay_expression | parameter_expression | .parameter_name(parameter_expression)
port_connection = expression, expression, ... | .port_name(expression), .port_name(expression), ...

Description:

An instantiation is used to define the design hierarchy by making a copy of a lower level module, primitive or UDP.

The # notation is used in two different ways: it specifies delays for primitive or UDP instances, or overrides the parameter values in a module instance. The parameters must be redefined in the same order they are declared within the module. In Verilog-2001 a named parameter redefinition notation can be used.

The optional instance range instantiates multiple modules, primitives or UDPs, each instance connected to separate bits of a vector.

The port connection can be an ordered or named list. In an ordered list the signal connection must be in the same order as the port list in the module. Unconnected ports are designated by two adjacent commas. In a named list, the names must correspond to the ports in the module. A named port connection is only allowed for module instances.

Arbitrary expressions may be used to connect to input ports, but output ports may only be connected to nets, bit or part selects of nets or concatenations of these. Input expressions create implicit continuous assignments.

The strength can be used only in UDP or primitive instances.

Example:

Dff #(4) u1 (.Clk(Clock), .D(D_In), .Q(Q_Out));
Dff u2 (Clock, D_In, Q_Out);
Cnt u3 (Clk, , A&&B, Q);
Nand (weak1, pull0) #(2) u4 (Q, A, B);

Notes:

• Use named connections to improve readability and reduce errors.
• Use only bit or part selects and concatenations for port expressions.

Ports in Verilog Module

Port_list is an important component of verilog module. Ports provide a means for a module to communicate with the external world through input and output. Every port in the port list must be declared as input, output or inout. All ports declared as one of the above is assumed to be a wire by default, to declare it otherwise it is necessary to declare it again. For example in the D-type flip flop we want the output to hold on to its value until the next clock edge so it has to be a register.

/*

module d_ff(q,d,reset,clock); // all ports must be declared as input or output

output q;

input d, reset, clock;

reg q; // the ports can be declared again as required

.......

endmodule

*/

Note: by convention, outputs of the module are always first in the port list. This convention is also used in the predefined modules in Verilog.

A different way ports can be declared as below other than the above one:

module d_ff(

output reg q,

input (d,reset,clock);

.......

endmodule