Verilog Design Structures

Vrit Raval

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VERILOG NOVICE TO WIZARD

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Aug 24, 2019

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Verilog Design Structures

A structure may be the entire file or there may be more than
one structure in a file. No less than a structure may be
in a file.

Verilog Design Structures

• file structure
• primitive structure
• configuration structure
• specify structure

file structure

File Structure  <compiler directives>  module ...        // zero or more module definitions
    <module contents>
  endmodule  macromodule ...   // zero or more macromodule definitions
    <macromodule contents>
  endmacromodule  primitive ...     // zero or more primitive definitions
    <primitive contents>
  endprimitive  config ...       // optional configuration specification
    <configuration statements>
  endconfig

module structure

The top of every design hierarchy must be a module.
The module that is never instantiated is the top of the design.The module structure defines the interface and the design.
Module Structure (same for macromodule)  module module_name(<port_name_list>); // (<port_name_list>) is optional
    input <some_port_names>;            // any port names that are inputs
    output <some_port_names>;           // any port names that are outputs
    inout <some_port_names>;            // any port names that are both    <parameters>                        // optional parameters and overrides    <specify block>                     // optional specify block    <declarations>                      // optional variable declarations and
                                        // optional net declarations    <function definitions>              // optional function definitions    <task definitions>                  // optional task definitions    <parallel statements>               // optional module instantiations
                                        // and parallel statements    initial                             // zero or more initial blocks
      begin
        <sequential statements>
      end    always                              // zero or more always blocks
      begin
        <sequential statements>
      end  endmodule // identifier               // physical end of module
  // add32.v  verilog 32 bit adder (Verilog 2001 style)
  module adder(input  [31:0] a,     // a input
               input  [31:0] b,     // b input
               input         cin,   // carry-in
               output [31:0] sum,   // sum output
               output        cout);  // carry-out
    parameter d=2;
    assign #d {cout, sum} = a + b + cin; // after d units of time
  endmodule // adder
  // add32.v  verilog 32 bit adder (pre Verilog 2001 style)
  module adder(a, b, cin, sum, cout);
    parameter d=2;
    input  [31:0] a;     // a input
    input  [31:0] b;     // b input
    input         cin;   // carry-in
    output [31:0] sum;   // sum output
    output        cout;  // carry-out
    assign #d {cout, sum} = a + b + cin; // after d units of time
  endmodule // adder

primitive structure

Also called UDP, for User Defined Primitive.  primitive identifier(<parameters>); 
    output <output identifier> ;
    input  <input identifier list> ;
    table
      <input to output transition table>
    endtable
  endprimitive // identifier  Output symbols:      0, 1, x, X
  Input level symbols: 0, 1, x, X, b, B, ?
  Input edge symbols:  f, F, n, N, p, P, r, R, *  primitive mux(out, ctrl, in1, in2); // sample primitive definition
    output out;
    input  ctrl, in1, in2;
    table // ctrl in1 in2 : out
              0    1   ?  :  1;
              0    0   ?  :  0;
              1    ?   0  :  0;
              1    ?   1  :  1;
              x    0   0  :  0;
              x    1   1  :  1;
              // other cases output x
    endtable
  endprimitive // mux

configuration structure

config  identifier;
     [ declarations , see allowed list below ]   -- optional
     [ statements , see allowed list below ]  
  endconfig   // identifier

specify structure

specify  identifier;
     [ declarations , see allowed list below ]   -- optional
     [ statements , see allowed list below ]  
  endspecify   // identifier