Verilog Events and Delay
Published in
2 min readSep 26, 2019
Contents
- Delays
- Events
Delays
Typical uses of delay #20; // delay 20 time units
#10 <statement> // the statement execution takes 10 time units
// (blocking, next statement waits the 10 time units)
#10 var <= expression; // non blocking statement, var takes 10 time units
// to update but next statement proceeds with no delay
#(12.5 : 15 : 18.2) <statement> // minimum : typical : maximum time units
#(12.5 : 15 ; 18.2 , 15.2 : 20.1 : 30) <statement>
//rising times, falling times each minimum : typical : maximum
#(3:4:5 ; 4:5:6 ; 5:6:7) <statement>
//rising times; falling times; transport times each having
minimum : typical : maximum and #5 (out, in1, in2, ...); // delay from input to output
and #(5,6) (out, in1, in2, ...); // rising and falling delay
and #(4:5:6) (out, in1, in2, ...); // min : typical : max delay
and #(4:5:6 , 5:6:7) (out, in1, in2, ...); // min:typ:max on rise and fall
buf #(4, 5 , 10) (out, in); // rising, falling, and transport delay
buf #(4:5:6 , 5:6:7 , 6:7:8) (out, in); // full timing specification
//rising times; falling times; transport times each having
minimum : typical : maximum
Events
Event triggers are of the form: @event_identifier statement; // trigger on event_identifier
@(event_expression) statement; // trigger on event_expression
@* statement; // trigger on any change
@(*) statement; // trigger on input changeTypical examples of event triggering always @reset_event // assumes a declaration event reset_event;
begin // triggered upon a -> reset_event;
<statements to reset the circuit>
end
always @(posedge clear or negedge clk or reset_event)
begin
<statements to be executed>
end
always @* // same as @(a or b or c or x)
begin
a = b + c;
d = a - funct(x);
end
always @(*) // same as @(b or c or x)
begin
a = b + c;
d = a - funct(x);
end
