Boundary Scan Architecture

Boundary Scan Architecture

The JTAG(Joint Test Action Group)/boundary-scan interface and technology is found in most of today’s electronics. The technology was standardized in 1990. May more standards have been added since then by building upon and enhancing this original standard to improve the testing of JTAG/boundary-scan. The use of the JTAG/IEEE P1149.1 Standard Boundary Scan Architecture is proposed as the basis for designing testable, defect-tolerant, VLSI processors.

In this fast-paced world the number of chips being fabricated is huge. The demand is so great that these chips are not being able to be produced that fast. Design, development and testing of these devices offer many challenges. Debugging the chip is another task which is very important and can be simplified if the designer is able to verify the operation of sub systems like ALU(Arithmetic Logic Unit) and RAM independently, also be able to control the MCU( Microprogram Control Unit) and be able to access data in private registers. After the design is taken care of it goes into the manufacturing phase where the main focus is on yields and tests. Manufacturing VLSI devices using aggressive tech ruins the yields, a solution to this problem is by using a low cost defect tolerance techniques. The Boundary-Scan (B-S) Architecture is used for designing VLSI processors. The B-S architecture provides a Test Access Port (TAP) which is used to control and repair the MCU as well as to control and observe key control and data values. Built-in Self-Test and B-S are used to solve the other test problems. The TAP can also be used to provide a measure of defect-tolerance.

Fig 1: TAP(Test Access Port)

Boundary Scan Architecture

Fig 2

This architecture defines the logic that is to be included in each chip, which helps in testing the system. As mentioned earlier it has a Test Access Port (TAP) which consists of a four-signal interface, a controller, an instruction register, and two or more test data registers (Figure 1). One of these test data registers is the B-S register. This register is formed by serially linking latches (which are part of a B-S cell) that are placed at each device I/O so that the signals at the I/O can be controlled and observed. The TAP is such a useful port it not only controls the B-S and other testability logic but it can be designed so as to provide the ability to serially read and write any register within the device. Its powerful capability can be used for applications other than test. The authors of this paper proposed using this for controlling and repairing of the MCU.


A control unit whose binary control variable are stored in memory is called a microprogrammed control unit. The MCU being referred to out here is based on a non-RISC (Reduced Instruction Set Computer) proposed by Wikes in 1951. It consists of a Control Memory (CM), which is organized as a read only memory. The address is obtained from the op-code of the instruction to be executed and external conditions. The word read out, is the microinstruction and contains control information in a encoded format, that activates the functional units so that the instruction is executed. These microinstructions also contains part of the address for the next set of microinstruction that are to be executed.

Fig 3: Typical MCU

To control the MCU, it must be modified by adding shadow registers or other means.

Fig 4: Modified MCU

Converting the microprogram data register into a JTAG UTDR (User Test Data Register) allows complete control of the information in the data register. Using the JTAG protocol, a microinstruction can be monitored or can change its value. The addition of two UTDRs to the MCU, and some control logic make it possible to repair or modify any microinstruction within the control memory. Built-in Self-Test (BIST) can be used as the primary methodology for ensuring the testability of the Processor. Test complexity has increased with growing functionality. The test strategy proposed reduces this complexity by a divide and conquer approach as the basis for enhancing the controllability and observability of the processor, and then adopting specific self-test techniques to provide autonomous testing of each module. This test proposed is just a general one and can be modified for different architecture.

Yield enhancement are very important, especially during the initial phase when the process is maturing and the product volume is ramping up. The JTAG architecture promises to provide a low cost interface to control redundancies and permit defect-tolerance. This can be used for other structures too.

This Boundary Scan architecture has been proven to be highly effective and was widely accepted and modified to make testing more effective.


Fig 1:

1] Zorian, Y., & Jarwala, N. (n.d.). Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture. Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors. doi:10.1109/iccd.1989.63432



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