Futuristic Improvements In Simulated Annealing

AAYUSH MEHTA
VLSI Cell Placement Techniques
2 min readJun 7, 2021

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Researchers have recently begun to use statistical approaches to examine the algorithm’s performance and modify its operational settings. When compared to prior versions, a tenfold speedup has been noted.

Each step in the unit step function and the six temperature functions was given the same amount of computing time. The Net Optimal Linear Arrangement issue, which is the one-dimensional version of the cell placement issue, was used to test these functions. All functions were given the same amount of computing time, and the cost savings were compared. The six temperature annealing, constant, and cubic difference functions had the best results.

The acceptance function is Tk, the prior and new costs are C and CJ, and the kth temperature step is Th.

This image has been cited from “VLSI Cell Placement Techniques”- by K. SHAHOOKAR AND P. MAZUMDER Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109

There is no preset start temperature TI. Rather, the starting temperature is selected to obtain xo, the required initial acceptance probability. If ml and mz are the number of perturbations that have resulted in cost reduction and increase, respectively, and the m2 cost-increasing perturbations are accepted using the Metropolis criterion, then the total number of configurations approved.

Predetermined temperature decrements were employed in most previous implementations, which aren’t ideal for all circuit layouts. Variable length Markov chains result from such a cooling strategy.

This image has been cited from “VLSI Cell Placement Techniques”- by K. SHAHOOKAR AND P. MAZUMDER Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109

This Blog has been published as a part of a blog series on the topic “VLSI Cell Placement Techniques” which is a Co-Curriculum activity in our college (Vishwakarma Institute Of Technology, Pune) which is aimed at giving the students a comprehensive understanding of the Industry Practices in the field of Digital Design. We hope this blog has been a informative read for you.

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AAYUSH MEHTA
VLSI Cell Placement Techniques

Just a GEM of the this world and still not valued. PS. (GEM = General Engineer Male)