Decimation Filter for Sigma-Delta Converters

Sigma-Delta converters are a necessity in any digital system because of their high switching speed and ability to process lots of continuous analog values. However, filter decimation in such Sigma-Delta converters proves to be a high cost operation owing to the large number of binary adders, multipliers, integrator and comparator circuits involved.

Traditional ways of dealing with this drawback involve:

a) improving the noise shaping characteristics in the modulator thereby reducing the sampling frequency leading to lower computational cost.

b) use of comb filters at the first stage of decimation to reduce the sampling frequency, followed by more complex filter structures, such as FIR filters and Wave Digital filters

Owing to development in VLSI technologies with low cost, lesser die area, high speed binary adders and multipliers has Sigma-Delta filter decimation become easier. In this proposed VLSI architecture, The control sequence of the decimation filter is coded in the form of amicroprogram with horizontalmicroinstructions. It ensures that the changes in the sampling rate and the propagation of data are handled correctly. Themicroprogram is generated from the multirate decimation filter structure by using a recursive algorithm.

For example, for a signal with bandwidth (fb) of 3.4 KHz, oversampled using a second order Sigma-Delta Modulator and input sampling frequency (1024kHz), the output sampling frequency f(k) at each stage k is given by,

Conversely, the stopband cutoff frequency fs (k) is selected such that atiasing is not allowed in the transition band for all stages except the final stage. The stopband cutoff frequency is

There are altogether 15 allpass filters in the 7-stage multirate decimation filter thereby needing 15 words to be allocated in the D-RAM. The first PRAF stage obtains its data from the input FIFO.

Such a recursive mechanism within the D-RAM is found to be flexible, efficient and requires either comparable or less register and arithmetic resources than other architectures. It is believed that the flexibility of the architecture would make it attractive as a standard module in an ASIC library for a variety of applications that require oversample A/D converters.

Mok, K. Y. F. (1994). A VLSI decimation filter for sigma-delta A/D converters. Second International Conference on `Advanced A-D and D-A Conversion Techniques and Their Applications’. doi:10.1049/cp:19940540