Implementation of VLSI Architecture in Application Specific CORDIC Processors

Any signal in Digital Signal Processing can be categorised as either:

Deterministic: one that follows a defined mathematical function

Random: one that cannot readily be expressed in mathematical notation.

Source: electricajournal.org/signals_and_systems/signals_classification

Even so, irrespective of its complexity, all Deterministic and even a few Random signals can be represented by a family of mathematical equations using trigonometric and conic equations. The CORDIC processor helps us realize these equations. The COordinate Rotation Digital Computer (CORDIC) algorithm is a hardware efficient iterative algorithm which allows a simple shift and add operation to calculate hyperbolic, exponential, and logarithmic and trigonometric functions like sine, cosine, magnitude and phase with great precision for Digital Signal Processing (DSP) applications especially during modulation and demodulation phases.

Source: media.latticesemi.com/products/designsoftwareandip/intellectualproperty/ipcore/ipcores02/cordic

However, despite all the buzz and talk surrounding the success of such a precise mathematical processor, the CORDIC algorithm has its fair few disadvantages. As number of gates and ROM memory required starts increasing at an alarming rate for any application, implementation of the CORDIC becomes increasingly difficult due to higher quantization errors. One of the suggested methods to deal with this issue is development of a proper Application Specific ‘pipeline’ in Verilog HDL. Such optimization not only saves area on silicon substrate but also helps in reducing the computed quantization error.

The proposed pipeline for a more general application is shown as follows:

The CORDIC architecture is efficiently coded using Verilog HDL. The architecture is pipelined to have an internal critical path of a single adder. To minimize angle approximations error, numbers of micro-rotations have been
adjusted. To reduce the total quantization error including scale factor error, the pipelined CORDIC architecture has been optimized.

VLSI Architecture Design and Implementation for Application Specific CORDIC Processor by Amritakar Mandal et al. 2010 IEEE International Conference on Advances in Recent Technologies in Communication and Computing